Where performance meets integration.

As demand grows for smaller, thinner, and more powerful devices, advanced wafer-level designs have become essential. Wafer Level Packaging (WLP) enables high performance and multifunctionality while maintaining tight form-factor and cost targets—addressing the manufacturing and integration challenges of today’s consumer, communications, and industrial electronics.

Inside the Technology

  • Wafer level packaging formats including Fan-in WLP (FIWLP) and Fan-out WLP (FOWLP)
  • Embedded component and interconnect technologies such as Integrated Passive Devices (IPD) and Through-Silicon Via (TSV)
  • Specialized package solutions including Encapsulated Chip Package (ECP) and RFID packaging

Technical Highlights

High-performance fan-out WLP (eWLB and ECP) delivering strong bandwidth, performance, size, and cost advantages
eWLB platform enables smaller footprints and higher I/O density for more efficient package designs
Millimeter-wave-optimized wafer-level AiP antenna solutions supporting improved high-frequency performance, shorter interconnects, lower conductor loss, and optimized dielectric properties
2D/2.5D/3D WLP integration—using side-by-side or stacked chips, embedded devices, and dual-sided RDL—to enable complex PoP and SiP solutions
Five-sided protection via FI-ECP and eWLCSP wafer-level technologies
BGBM packaging—wafer-thinning plus backside metallization—to enhance thermal diffusion, electrical performance, and reduce impedance for MOSFETs, IGBTs, and other vertical-structure devices

Applications

5G Mobile
Processors
Wi-Fi Routers &
Power Amplifiers
Wearable Devices
AI & Enterprise
Servers
Communication
Infrastructure
Processors

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