2.5/3D Packaging | STATS ChipPAC

Architecture beyond the planar.

Advanced 2.5D and 3D packaging stacks and interconnects multiple components to maximize functionality and performance.

Inside the Technology

Package Level Integration

Stacked Die (SD) enables compact multi-die designs
Package-on-Package (PoP) stacks memory and logic packages
Package-in-Package (PiP) integrates packaged and bare chips into FBGAs

Wafer Level Integration

3D wafer level packaging (WLP) with redistribution layers
eWLB supports high-density connections in 2D, 2.5D, and 3D
eWLCSP™ enhances CSP reliability, while WLCSP improves density

Silicon Level Integration

3D IC design eliminates interposers and substrates
2.5D eWLB enables dense interconnects without TSVs
2.5D MEOL uses TSVs for cost-effective, high-volume integration

Explore All Technologies

Wirebond Packaging

Reliable, cost-effective interconnects trusted in high-volume manufacturing

Flip Chip Packaging

High-density, high-performance interconnects for advanced miniaturization

Wafer Bumping

Foundational process technology for high-yield advanced packaging

Wafer Level Packaging

Advanced performance in ultra-compact form factors

System-in-Package (SiP)

High-density integration without trade-offs in performance or footprint

MEMS & Sensors Packaging

Compact, integrated packaging for intelligent sensing and control

2.5/3D Packaging

Higher density, better performance, and more efficient integration