Utilises wire bond and flip chip connections to stack bare dies in standard packages. Common configurations include FBGA-SD, FLGA-SD, PBGA-SD, QFP-SD, and TSOP-SD.
Stacks fully tested memory and logic packages, simplifying IC technology integration. Options include Bare Die PoP, Molded Laser PoP, and PoP-MLP-ED for enhanced flexibility.
Combines packaged and bare chips into a single JEDEC standard FBGA, maintaining a compact footprint while enabling diverse functionalities.
A versatile Fan-Out embedded Wafer Level BGA platform that reduces substrate complexity and cost. It supports high-performance applications with compact package sizes and reliable interconnections.
Utilises the Fan-out process, known as the FlexLine™ method, to deliver a robust and reliable package with higher density and improved performance.
Standard Wafer Level CSP packages incorporate low-cure temperature polymers and copper for under-bump metallization, ensuring higher package reliability.
Features eWLB-based interposers for effective heat dissipation and improved processing speed. This approach minimises costs and streamlines the supply chain while supporting a transition to more advanced packages.
Utilises TSV integration to enable high-volume manufacturing at a commercially viable cost. Collaborative efforts with leading foundries and customers have enhanced the scalability and efficiency of this technology.
