Wafer Bumping Services

Wafer Bumping Services

Wafer Bumping


Wafer bumping technology can provide significant performance, form factor and cost advantages in a semiconductor package. We offer wafer bumping for both 200mm and 300mm wafer sizes in a range of options including printed bump, ball drop and plated technology with eutectic, high lead, lead free and copper column alloys. Our wafer bumping offering includes wafer bump and redistribution, full turnkey services for advanced Flip Chip applications and full turnkey services for Wafer Level Chip Scale Packages (WLCSP).



Wafer Level Packaging

Whether it be lightweight mobile electronic devices, large fixed systems or high performance devices, there is an insatiable demand for the smallest, lightest devices that can also offer the highest performance and reliability. One solution to meet the needs of these demanding size and performance requirements is to focus on the smallest complete package available, which is the die itself. The most compact method of connecting the device to the external world and other similar compact devices is wafer level packaging.

These types of die size packages cover a variety of packaging technologies:
  • Wafer Level Chip Scale Packages (WLCSP)
  • Wafer Scale Packages (WSP)
  • Chip Scale Packages (CSP)
  • Flip Chip Packages

These packages cover the complete range of die sizes, from <1.0mm square up to 20mm square. In addition, all of these devices require a simple electrical and mechanical connection between the active circuitry of the die and the substrate or circuit board to which it is attached in order to communicate with other devices. To achieve this connectivity, miniature metal solder balls (also called bumps or pillars) are used to create the connection between the electronic device and the substrate.

Solder Ball Materials

The factors governing the choice of bump material go beyond the nature of the bump itself. Needless to say, it is critical that the metal solder bumps used in wafer level packaging demonstrate both high electrical and high mechanical reliability during the lifetime of the product. Solder balls are available in a variety of metal combinations, and can be formed using a variety of processes, depending on the alloy and feature size. Metal combinations include:
  • Sn63/Pb37 Eutectic
  • Sn5/95Pb High-Lead
  • Sn/Ag/Cu (SAC) Alloys
  • Sn97.5/Ag2.5
  • Metal Cu columns or Cu columns capped with one of the previously mentioned solders

Bump Development

Bump/Pitch Description Alloy Solution
Small, fine pitch bumps of single or binary alloys Plating
Medium diameter and pitch sizes
  • Bump diameter: 90~130µm
  • Array pitch: 175 to 300µm
  • SAC alloy formulations
Screen printed paste
Largest diameters and pitches
  • 250~350µm diameter
  • 400~600µm array pitch
Solid spheres or ball drop
Solder or metal-coated polymer spheres

Bump Array Pitch

Typically arranged in a grid array pattern, the array pitch of solder balls used in wafer level packaging can vary from a minimum of 150µm to 600µm. Bumps diameter can also vary, and can range from diameters of 80µm to 350µm.
 

Interconnection Technology: Wafer Level CSP vs Flip Chip

Method of attachment of the device to the board or substrate also vary and determine the type of technology that is employed.
 

Printed Interconnect and WLCSP

This combination of bump pitches, bump diameters and device sizes, make it possible to attach some devices directly to a circuit board without any further adhesion enhancement in a manner similar to that used for any surface mount overmolded package such as QFN, SOT or CSP. This method of attachment is limited to small (typically <20mm2) die and employs the larger bump or ball connections and pitches and is generally referred to as WLCSP Packaging.
 

Plated Interconnect and Flip Chip

The alternative method of attachment to a board or substrate employs the use of an underfill material in the open spaces around the bumps and in the gap between the surface of the die and the circuit board. This enables reliable application of the largest die with bumps with minimum diameter and pitch. When used in this format, the application is typically referred to as Flip Chip Packaging. The most efficient implementation of Flip Chip technology occurs when the bump sits directly over the electronic cells to which they are connected (bump on I/O).
 

Redistribution Layer (RDL) and Re-Passivation

In situations where additional die protection is required, or situations where additional structural support is required at the bump location, a single layer of polymer and metal is applied to the wafer. This process is referred to as re-passivation (RPV) since the addition of the polymer layer creates a second layer of passivation on the surface of the die.

In situations where a device may have to function in both a wire-bondable peripheral pad arrangement or as a Flip Chip or Wafer Level component, an additional layer of lateral connections may be employed to rearrange the peripheral wirebond connections in a manner suitable for Wafer Level Processing. This additional layer is known as a Redistribution Layer or RDL and may be fabricated from a thin layer of Al, AlCu or Cu.
 

Integrated Passive Devices (IPD)

By using RDL, Metal Deposition and Passivation technologies in conjunction with each other, it’s possible to create miniature, low value passive devices, i.e., Resistors, Capacitors and Inductors on blank silicon wafers or on top of the die on an existing wafer. The devices created using this process are called Integrated Passive Devices (IPD).

IPD electrical connections, bumps or bumps with RDL are the backbone of Wafer Level Processing, Wafer Bumping and Die Level Interconnection technology.
 

Die Attach Capabilities: Flip Chip vs. Wirebond

Further enhancing our turnkey capabilities are our test sites in Singapore, Taiwan, Korea and China where STATS ChipPAC is capable of taking internally or externally bumped wafers and providing a further level of integration by attaching the Flip Chip die to substrates, either singly or in combination with other Flip Chip or wire bondable devices, passive components including ISP devices, to form even more complex and equally reliable multichip modules.
 

Full Turnkey Wafer Level Services at STATS ChipPAC

STATS ChipPAC can lower both cost and cycle time by offering full turnkey test and packaging capabilities for a broad spectrum of wafer bumping related processes, including:
  • wafer bumping and redistribution services
  • full turnkey services for advanced Flip Chip applications
  • full turnkey services for Wafer Level Chip Scale Packages (WLCSP)

Available Features and Services

Features & Services Details
Wafer Sizes (mm) 150mm, 200mm, 300mm
Bump Technology Paste Print (150mm, 200mm)
Ball Drop (150mm, 200mm)
Plated Bump (200mm, 300mm)
IPD Capability AlCu/Plated Cu (200mm)
Min Bump Pitch (μm) 150μm
Bump Height (μm) Small bump / fine to medium pitch: Min: 70μm, Max: 140μm
Large bump / medium to large pitch: Min: 250μm, Max: 350μm
Bump Alloys Hi-Pb (95Pb/5Sn) Plated
Eu (63Sn/37Pb) Plated
Pb Free (97Sn/2.5Ag) Plated
Eu (63Sn/37Pb) Printed Paste
Printed Paste: SAC-405, 305
Ball Drop: Eu, SAC-405, 305, 105
Pb Free (CuPillar + 97Sn/2.5Ag) Plated
Low α Alloys
Repassivation (μm) PI (Rep/RDL) HD4100
PI (Cu-RDL) HD4110
UBM   Ti/NiV/Cu (PI)
Al/NiV/Cu (FOC over SiO/SiN Pass)
Ti/NiV/Cu (FOC over PI Pass)
Ti/Cu/Cu/Ni (Plated Bump)
RDL Ti/AlCu (150mm, 200mm)
Ti/Cu/Plated Cu (Cu-RDL) (200mm)
2 Layer RDL (IPD Products)
Bumping Capacity (KW/Mo)  6, 10, 11
Wafer Probe Test  Available
Back End Outgoing Optical Inspection
Mark (laser)
Back Grind
Saw Singulation
Tape & Reel (with Visual Inspection)
Ship on Rings