Final Test

Final Test Floor at STATS ChipPAC Singapore (SCS) with 10k Clean Room Environment

  Next Generation Test Cell 

In a primitive form of Final Test, a test cell is composed of a handler, a tester and a tester workstation that communicates with the handler over a GPIB, parallel or serial communications interface. Within this test cell, an operator divides his time between multiple testers, performing many tasks and, when or if time allows, checks whether any testers are running out-of-control.

In contrast, STATS ChipPAC has evolved to a Next Generation Test Cell that includes an Automatic Test Cell Controller and a Tester Utilization Tracking System connected to the communications interface between tester and handler that monitors all the activity between tester and handler (see photo below).

The Tester Utilization Tracking System automatically captures the actual, real-time tester utilization where productive time is actual test time + actual index time and all other time is a category of waste. Utilization trends are displayed on a utilization monitor next to the tester workstation.

At the same time, the Automatic Test Cell Controller is continuously monitoring the good yield, the yield variation between test sites and the failure rates for all hard and soft bins looking for pre-defined out-of-control events. When it detects an out-of-control event, the Auto Controller automatically stops the tester and activates an alarm to immediately bring line support technicians into the test cell to fix the problem.

This Next Generation Test Cell also includes a scanner to avoid manual entry mistakes. Test hardware used in production at STATS ChipPAC is bar-coded along with the Lot ID on the Lot Traveler.

This Next Generation Test Cell enables automatic closed loop process control, which STATS ChipPAC utilizes to keep test manufacturing processes under control at all times.

At the core of a Final Test cell is a test platform and a handler. The following table highlights the primary handling equipment used at Final Test in STATS ChipPAC.

Other types of handling equipment are available at STATS ChipPAC factories to satisfy special customer requests. Contact STATS ChipPAC to request other handlers not highlighted in the table.

For package body sizes less than 3×3 mm, STATS ChipPAC recommends either a turret handling solution or a strip test solution. STATS ChipPAC’s turret handlers integrate tape and reel creating a continuous manufacturing flow from Final Test into Post Test to improve throughput.

STATS ChipPAC offers sophisticated Burn-In systems with deep vector memory for dynamic Burn-In. Vector memory enables high fault coverage during the Burn-In process. JTAG testing and boundary scan can also be performed during Burn-In.

STATS ChipPAC has established close working relationships with subcontractors whose core business is Burn-In. By extending its Burn-In capabilities to include outside Burn-In specialists, STATS ChipPAC can take advantage of proprietary technology, techniques and Burn-In patterns from these vendors to satisfy any special customer requirements.