Flip Chip CSP

Flip Chip Chip Scale Packages (fcCSP)

STATS ChipPAC’s fcCSP packages form a subgroup of the Flip Chip package family of the form factor known as Chip Scale Packages (CSP). STATS ChipPAC offers a complete fcCSP portfolio of high to low-end leading edge packages for all mobile applications including standard fine pitch fcCSP packages, hybrid flip chipand fcPoP including Bare Die fcPoP and Molded Laser PoP (PoP-MLP).

Standard fcCSP

STATS ChipPAC’s standard fcCSP packages offering includes very thin profile packages (fcTCSP, fcVCSP, fcWCSP and fcUCSP), as well as side-by-side die configurations. All fcCSP packages are produced on substrates with matrix strip format and use overmolding and saw singulation processes similar to wirebond packages of the same form factors. The fcCSP is an overmolded package with solder balls, and is available in a high thermal performance package (fcCSP-H) produced on substrates in matrix strip format with heat spreader.

Hybrid fcCSP

fcFBGA packages are also available in very thin profile hybrid flip chip (flip chip on the bottom and wirebond die on the top) such as fcTCSP-SD2 andfcTCSP-SD3. Hybrid fcCSP packages are available with Mass Reflow (MR), CUF or MUF, and copper (Cu) pillar and Cu wire.

fcPoP

STATS ChipPAC’s fcFBGA offering also includes package-on-package (PoP) solutions in Bare Die and Molded Laser formats. Both fcPoP formats are offered as the bottom PoP package (PoPb) of a stackable flip chip BGA. PoPb is typically an application processor or an integrated baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. Bare Die PoP differs from fcBGA through the inclusion of memory interface (MI) pads on the substrate top side. Molded Laser PoP (MLP) offers aggressive package height reductions or 0.35mm MI pitch, and, with its overmold configuration, provides better warpage performance. MLP-PoP is also offered with an exposed die (PoP-MLP-ED) which reduces mold cap height and improved warpage performance.

Features

Body sizes 4 x 4mm through 17 x 17mm
Electroplated Eutectic SnPb, hi-Pb or Pb-free bumps or Cu column
Bumping capability down to
130µm pitch with lead-free solder and pitch down to 40µm with Cu column
Full service wafer bumping with BCB and Polyimide dielectric options for wafer repassivation and redistribution layer (RDL)
Molded underfill (MUF) or Capillary underfill (CUF) options
Uniquely developed fcCuBE MR process supports bump pitches down to
80µm and below, providing a lower cost alternative to TCB
Thermal-Compression Bonding with Non-conductive Paste (TCNCP) available
MUF with solder bump and Cu column qualified and in production
0.40mm min. package ball (BGA) or pad (LGA) pitch in production
145 Μ m minimum die solder bump pitch in production
BGA pitch down to 0.35mm qualified and in production
Maximum overall height of 1.40mm (fcLCSP); 1.20mm (fcTCSP); 1.00mm (fcVCSP); 0.65mm (fcLGA)
Conventional 2 to 6 layer through-hole or PPG build-up laminate substrates available; ABF build-up substrates available
Low cost substrate technology options including Embedded Trace Substrate (ETS) in HVM, and Via Under Trace (VUT) qualified, No-Clean Flux and Non-PI Bumping qualified or HVM, and others such as large die CUF and Land Side Cap (LSC) with 0.4mm BGA pitch in development One piece heat spreader option for exceptional thermal performance; fcCSP-ED-H (1-piece heat spreader) with MUF qualified
Packages assembled in either bare die, exposed die and overmolded strip matrix format, and saw singulated; high density wide strip available

Applications

STATS ChipPAC offers a complete fcFBGA portfolio of high to low-end packages for all mobile applications:

Mobile processors for Smart Phones, Tablets and Wearable Electronic (WE) devices including baseband, application processors, and application processors + baseband
Chipsets for peripheral IC’s driven by demand for high-end Smart Phone functionality, including RFIC, PMIC, Connectivity, Sensors/ MEMS, and Audio CODEC

Additional Resources

This post is also available in: Chinese (Simplified)

Flip Chip CSP

Flip Chip Chip Scale Packages (fcCSP)

Standard fcCSP

Hybrid fcCSP

fcPoP

Features

Body sizes 4 x 4mm through 17 x 17mm

Electroplated Eutectic SnPb, hi-Pb or Pb-free bumps or Cu column

Bumping capability down to

Full service wafer bumping with BCB and Polyimide dielectric options for wafer repassivation and redistribution layer (RDL)

Molded underfill (MUF) or Capillary underfill (CUF) options

Uniquely developed fcCuBE MR process supports bump pitches down to

Thermal-Compression Bonding with Non-conductive Paste (TCNCP) available

MUF with solder bump and Cu column qualified and in production

0.40mm min. package ball (BGA) or pad (LGA) pitch in production

145 Μ m minimum die solder bump pitch in production

BGA pitch down to 0.35mm qualified and in production

Maximum overall height of 1.40mm (fcLCSP); 1.20mm (fcTCSP); 1.00mm (fcVCSP); 0.65mm (fcLGA)

Conventional 2 to 6 layer through-hole or PPG build-up laminate substrates available; ABF build-up substrates available

Packages assembled in either bare die, exposed die and overmolded strip matrix format, and saw singulated; high density wide strip available

Applications

Mobile processors for Smart Phones, Tablets and Wearable Electronic (WE) devices including baseband, application processors, and application processors + baseband

Chipsets for peripheral IC’s driven by demand for high-end Smart Phone functionality, including RFIC, PMIC, Connectivity, Sensors/ MEMS, and Audio CODEC

Additional Resources

fcCSP Datasheet

fcCuBE datasheet

Bare Die fcPoP datasheet

Molded Laser fcPoP datasheet

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