R&D Facility for Next Generation Integration Technology
STATS ChipPAC is the first OSAT service provider to establish a dedicated next generation wafer level integration R&D facility. Located at Woodlands Spectrum 1 Industrial Estate in Singapore, the STATS ChipPAC Woodlands R&D facility is dedicated to developing next generation technology including through silicon via (TSV) and microbump bonding for 3D die, silicon substrate based packaging solutions and embedded active die technology.
Equipped with state-of-the-art FOL equipment, this cutting edge 51,129 square foot R&D operation includes over 10,000 square feet of Class 10, 100 and 10K cleanroom space with an additional 9,000 square feet of space available for future expansion.
Specializing in advanced wafer level processing, the Woodlands R&D facility features an equipment set for photolithography, plasma etching and deep reactive ion etching (DRIE), wafer thinning and wafer bonding.
Through Silicon Via (TSV)
TSV is the process of creating contact via in silicon in order to establish an electrical connection from the active side to the backside of the die, thus creating options for 3D integration. Embedded die technologies are for next generation System-in-Packages (SiP) that enable a higher level of integration in a smaller form factor.
The Woodlands R&D operation will provide next generation IPDs as well as TSV and microbump bonding methods for 3D die and silicon substrate based system-in-package (SiP) solutions.