JCET Enters Into Strategic Business Agreement with Analog Devices to Grow Singapore Test Business

Singapore – December 24, 2019 – JCET Group Co., Ltd (‘JCET’) has entered into a strategic business agreement with Analog Devices Inc. (‘ADI’) in which JCET will acquire ADI’s test facility in Singapore. As part of this agreement, JCET will take on additional ADI test business in this newly acquired facility. The final transfer of ownership of the ADI Singapore test facility to JCET will be completed May 2021.

“This agreement with our long time assembly and test partner JCET will allow ADI to take advantage of the operational and test engineering expertise we have experienced for many years as a customer in their Singapore plant” stated Steve Lattari, Senior Vice President of Global Operations and Technology at ADI. “We anticipate a smooth transition as we work together to make this new part of our relationship happen,” continued Lattari.

“ADI has been a highly valued and long standing customer of JCET. This opportunity to both grow our test floor footprint in Singapore and more importantly our business with ADI is a win-win for our companies,” stated Li Zheng, CEO of JCET Group. “JCET’s investment in this Singapore facility also shows that as a multinational semiconductor company, we will continue to steadily strengthen our global expansion and provide first-class integrated circuit products and advanced technical services to international and local customers,” continued Mr. Zheng.

JCET Group has six factories located in China, Singapore and Korea. Its Singapore facility was established in 1994 as the first Outsourced Semiconductor Assembly and Test (OSAT) provider in Singapore.  JCET Singapore’s test services include wafer sort, final package test, strip test, wafer bump and all wafer level products.

Forward-Looking Statements

Certain of the statements in this release, including statements regarding the Company’s intellectual property, are forward-looking statements that are based on management’s current views and assumptions and involve a number of risks and uncertainties which could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chains; disruption of our operations and other difficulties related to the relocation of our China operations; loss of directors, key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or canceling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop  and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; beneficial ownership by JCET Group Co., Ltd. (“JCET”) of all of our ordinary shares that may result in conflicting interests with other holders of our securities; our inability to capture all or any of the benefits from acquisitions and investments in other companies and businesses or from the acquisition of us in August 2015 by JCET-SC (Singapore) Pte, Ltd., which is now wholly-owned by JCET; loss of customers or failure to compete effectively with our former Taiwan subsidiaries which we have divested in 2015; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks. All our forward looking statements are expressly qualified in their entirety by the cautionary statements set forth above. You should not unduly rely on such forward-looking statements, which speak only as of the date of this release. JCET does not intend, and does not assume any obligation to update any industry information or forward-looking statements to reflect subsequent events or circumstances. In light of these risks, uncertainties and assumptions, any of the events anticipated in these forward-looking statements might not occur.

About JCET

Founded in 1972, JCET Group Co., Ltd. (“JCET”) is one of the top semiconductor packaging and test providers in the world and the largest provider in China. With full turnkey services encompassing design and characterization, wafer bump, packaging and test, JCET is a strategic partner for semiconductor companies across a broad range of markets and applications. The comprehensive packaging portfolio of JCET and its subsidiaries include discrete, leaded, laminate, flip chip, Molded Interconnect System, wafer level packaging and System-in-Package technologies. Headquartered in Jiangyin, Jiangsu, China, JCET has an extensive global manufacturing base with operations in China, Singapore and South Korea. JCET is a publicly-traded company that is listed on the Shanghai Stock Exchange. Further information is available at www.jcetglobal.com.

Media Contact:

Christopher Stai
Deputy Director, Marketing Communications
Tel: (209) 534-6398
email: christopher.stai@statschippac.com

JCET Announces English Name Change to JCET Group Co., Ltd.

Jiangyin, November 18, 2019 – JCET announced it has received Shareholder approval to change its English name from Jiangsu Changjiang Electronics Technology Co., Ltd. and Jiangsu Changdian Technology Co., Ltd. to JCET Group Co., Ltd.  Founded in 1972, JCET is an Outsourced Semiconductor Assembly and Test (OSAT) company headquartered in Jiangyin, China. Through organic growth and acquisitions, JCET has become a leading international semiconductor company with the third largest revenue in the global IC packaging and test industry. As part of its global brand strategy, the change of the English name will enable JCET to establish a more outstanding corporate image that is a better fit for the company’s market strategy and business development needs. This name change will not affect the company’s operations. The rights and obligations of all customers and partners of JCET will also remain intact.

About JCET Group
JCET Group is a leading global semiconductor packaging and test provider, offering a full range of turnkey services that include semiconductor package design and characterization, R&D, wafer probe, wafer bumping, package assembly, final test and drop shipment to vendors around the world.
Our comprehensive portfolio covers a wide spectrum of semiconductor applications including mobile, communication, compute, consumer, automotive and industry etc., through advanced wafer level packaging, 2.5D/3D, System-in-Package, flip chip and wire bonding technologies. JCET Group has three R&D centers, six manufacturing locations in China, Singapore and Korea, and sales centers around the world providing close technology collaboration and efficient supply-chain manufacturing to customers in China and throughout the world.

Media Contact:
Christopher Stai
Tel: (209) 534-6398
Email: cstai@statschippac.com

JCET Group appoints Zhou Tao as CFO

JCET Group Appoints Janet Tao Chou As Cfo, With Mu Haoping To Now Serve As Senior Vice President For Capital Operations

SHANGHAI, October 16, 2019 /PRNewswire/ — JCET Group Co., Ltd (‘JCET Group’) today announced a new senior management appointment. Approved by the board of directors, Ms. Janet Tao Chou was appointed Chief Financial Officer, replacing Mr. Mu Haoping. Mr. Mu will now serve as Senior Vice President for Capital Operations and play an important role in capital management and major project investments, mergers and acquisitions.

Prior to joining JCET Group, Ms. Janet Tao Chou was Global Vice President of NXP Semiconductors, CFO of NXP Semiconductors Greater China and CFO of NXP Mobile device & IT Department. She also served as Finance Director of ON Semiconductor and California Microelectronics (acquired by ON Semiconductor). She holds a bachelor’s degree in accounting from the University of Texas, San Antonio and an MBA from Santa Clara University, California.

Mr. Zheng Li, CEO of JCET Group, stated, “Ms. Janet Tao Chou has tremendous experience in international finance as well as excellent management experience. We welcome her to our team and look forward to the enhancements she will bring at the financial management level while providing strong support for the company’s development.”

About JCET Group

JCET Group is a leading global semiconductor system integration packaging and test provider, offering a full range of turnkey services that include semiconductor package integration design and characterization、R&D、wafer probe、wafer bumping、package assembly、final test and drop shipment to vendors around the world.

Our comprehensive portfolio covers a wide spectrum of semiconductor applications such as mobile, communication, compute, consumer, automotive and industry etc., through advanced wafer level packaging、2.5D/3D、System-in-Packaging、and reliable flip chip and wire bonding technologies. JCET Group has three R&D centers, six manufacturing locations in China、Singapore and Korea, and sales centers around the world, providing close technology collaboration and efficient supply-chain manufacturing to customers in China and around the world.For more information, please visit www.jcetglobal.com.

Media Contact:

Danni Yu
Tel: (86) 510-86199586
email: danni.yu@cj-elec.com

CEO - Li Zheng

JCET Group Appoints Zheng Li as CEO, and Dr. Choon Heung Lee Will Continue to Serve as Chief Technology Officer

JIANGYIN, September 9, 2019 /PRNewswire/ — Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) today announces the appointment of Zheng Li as Chief Executive Officer and nominates as Director, replacing Dr. Choon Heung Lee, who will continue to serve as Chief Technology Officer and devote himself to the company growth.

Zheng Li has more than 26 years of experience in the IC industry. Prior to joining JCET, he served as SVP of NXP Semiconductors for Greater China and SAPAC, and President of NXP China. Before NXP, he served several management positions as SVP global marketing for SMIC and CEO of Renesas Greater China.

He received his Bachelor of Engineering degree from Tianjin University in Industrial management engineering, Master degree in financial Economics from the University of Tokyo in Japan. Zheng Li is currently Board of Director of China Semiconductor Industry Association, and is a part-time professor of Tianjin University in Microelectronics.

About JCET – JCET Group is the largest OSAT (Outsourced Semiconductor Assembly and Test) services provider in China and the third largest in the world. As a global OSAT, JCET Group provides a full range of turnkey services that include semiconductor package design and characterization, wafer probe, wafer bumping, package assembly, final test and drop shipment to semiconductor vendors around the world. Our global footprint centers around three regional manufacturing locations: Singapore, South Korea and China which collectively span almost the entire range of product offerings servicing both our domestic customers in China as well as North America and Europe.

New JCET 12 Inch Wafer Bumping Line in Advanced Flip Chip South Korea Factory Ramps into High Volume

Incheon, South Korea – July 29, 2019 – Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) has moved into volume production with its new 12 inch wafer bumping line which is located in Class 100 and Class 1000 clean room space in its state of the art assembly and test facility in Incheon, South Korea. Production volumes are already being shipped to JCET customers with several additional leading industry device manufacturers qualifying the line for shipments over the next few quarters.

Automotive, wireless, computing and other devices have already been qualified on this new bumping line which has now become an integral part of JCETs advanced flip chip packaging offerings in Korea. The line currently offers both lead free and copper column bump types with bump pitches as tight as 90um and down to 40um possible.

“We are proud to offer an additional source for bumping within the JCET group of factories” stated JCET CEO, Dr. Choon Heung Lee. “The demand for bumping services as part of a full turnkey assembly and test solution continues to grow exponentially and this new line enables us to provide this value added service at two of our regional manufacturing hubs,” continued Dr. Lee.

JCET’s campus in South Korea opened in 2015 and is a short drive from Incheon International Airport. This campus’ manufacturing facilities provide assembly and test of Flip Chip, Package-on-Package (PoP), Wafer-Level and Advanced System-in-Package solutions. JCET is the largest OSAT in China and the third largest in the world with factories in China, South Korea and Singapore.

Forward-Looking Statements

Certain of the statements in this release, including statements regarding the Company’s intellectual property, are forward-looking statements that are based on management’s current views and assumptions and involve a number of risks and uncertainties which could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilization; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chains; disruption of our operations and other difficulties related to the relocation of our China operations; loss of directors, key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or canceling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; beneficial ownership by Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) of all of our ordinary shares that may result in conflicting interests with other holders of our securities; our inability to capture all or any of the benefits from acquisitions and investments in other companies and businesses or from the acquisition of us in August 2015 by JCET-SC (Singapore) Pte, Ltd., which is now wholly-owned by JCET; loss of customers or failure to compete effectively with our former Taiwan subsidiaries which we have divested in 2015; labor union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks. All our forward looking statements are expressly qualified in their entirety by the cautionary statements set forth above. You should not unduly rely on such forward-looking statements, which speak only as of the date of this release. JCET does not intend, and does not assume any obligation to update any industry information or forward-looking statements to reflect subsequent events or circumstances. In light of these risks, uncertainties and assumptions, any of the events anticipated in these forward-looking statements might not occur.

About JCET

Founded in 1972, Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) is one of the top semiconductor packaging and test providers in the world and the largest provider in China. With full turnkey services encompassing design and characterization, wafer bump, packaging and test, JCET is a strategic partner for semiconductor companies across a broad range of markets and applications. The comprehensive packaging portfolio of JCET and its subsidiaries include discrete, leaded, laminate, flip chip, Molded Interconnect System, wafer level packaging and System-in-Package technologies. Headquartered in Jiangyin, Jiangsu, China, JCET has an extensive global manufacturing base with operations in China, Singapore and South Korea. JCET is a publicly-traded company that is listed on the Shanghai Stock Exchange. Further information is available at www.jcetglobal.com.

Media Contact:

Christopher Stai

Deputy Director, Marketing Communications

Tel: (209) 534-6398

email: christopher.stai@statschippac.com

JCET Group Appoints Distinguished Semiconductor Industry Executive Dr. Lee Choon Heung as CEO

China – Sept. 28, 2018, – STATS ChipPAC Pte. Ltd. (“STATS ChipPAC” or the “Company”), a leading provider of advanced semiconductor packaging and test services, announced Friday that the Board of Directors of its holding company, Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) has appointed Dr. Lee Choon Heung as Chief Executive Officer (‘CEO’) for JCET Group, as well as Chief Executive Officer and Chairman for STATS ChipPAC.

 

Dr. Lee brings to JCET a wealth of expertise and veteran leadership with 20 years of extensive semiconductor packaging and test experience. Dr. Lee served in several senior management positions at Amkor Technology Inc. including head of their R&D centre, head of global procurement, group vice president, senior vice president and Chief Technology Officer. Dr. Lee, holds a Ph.D. in Theoretical Solid State Physics from Case Western Reserve University, currently holds 59 industry patents, and has published 19 academic papers around the world.

“We are excited about the opportunity to bring on board an industry leader of the calibre of Dr. Lee Choon Heung as our new JCET Group CEO” stated JCET Chairman, Mr. Wang Xinchao. “We are confident in his ability to lead JCET as we continue our growth in both technology and scale moving forward,” continued Mr. Wang. Mr. Wang will continue in his role as Chairman of JCET Group.

 

The JCET Board of Directors and the management team also expressed their utmost gratitude and appreciation to Dr. Han Byung Joon and Mr. Lai Chih-Ming for their outstanding leadership and valuable contributions during their tenure at STATS ChipPAC. Dr. Han is resigning as chairman of the board of STATS ChipPAC. Mr. Lai will now serve in a new role as executive vice president of JCET Group.

Forward-Looking Statements

 

Certain of the statements in this release, including statements regarding the Company’s intellectual property, are forward-looking statements that are based on management’s current views and assumptions and involve a number of risks and uncertainties which could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chains; disruption of our operations and other difficulties related to the relocation of our China operations; loss of directors, key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop  and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; beneficial ownership by Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) of all of our ordinary shares that may result in conflicting interests with other holders of our securities; our inability to capture all or any of the benefits from acquisitions and investments in other companies and businesses or from the acquisition of us in August 2015 by JCET-SC (Singapore) Pte, Ltd., which is now wholly-owned by JCET; loss of customers or failure to compete effectively with our former Taiwan subsidiaries which we have divested in 2015; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks. All our forward looking statements are expressly qualified in their entirety by the cautionary statements set forth above. You should not unduly rely on such forward-looking statements, which speak only as of the date of this release. STATS ChipPAC does not intend, and does not assume any obligation to update any industry information or forward-looking statements to reflect subsequent events or circumstances. In light of these risks, uncertainties and assumptions, any of the events anticipated in these forward-looking statements might not occur.

About STATS ChipPAC Pte. Ltd.

 

STATS ChipPAC Pte. Ltd. is a leading service provider of semiconductor packaging design and characterization, wafer bump, assembly and test solutions for diverse end market applications in communications, digital consumer, computing and automotive electronics. Headquartered in Singapore, STATS ChipPAC has design, research and development, manufacturing and customer support offices throughout Asia, the United States and Europe. STATS ChipPAC is a member of the JCET Group of companies. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

 

About JCET

 

Founded in 1972, Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) is one of the top semiconductor packaging and test providers in the world and the largest provider in China. With full turnkey services encompassing design and characterization, wafer bump, packaging and test, JCET is a strategic partner for semiconductor companies across a broad range of markets and applications. The comprehensive packaging portfolio of JCET and its subsidiaries include discrete, leaded, laminate, flip chip, Molded Interconnect System, wafer level packaging and System-in-Package technologies. Headquartered in Jiangyin, Jiangsu, China, JCET has an extensive global manufacturing base with operations in China, Singapore and South Korea. JCET is a publicly-traded company that is listed on the Shanghai Stock Exchange. Further information is available at www.jcetglobal.com.

Media Contact:

Christopher Stai

Deputy Director, Marketing Communications

Tel: (209) 534-6398

email: christopher.stai@statschippac.com