China – Sept. 28, 2018, – STATS ChipPAC Pte. Ltd. (“STATS ChipPAC” or the “Company”), a leading provider of advanced semiconductor packaging and test services, announced Friday that the Board of Directors of its holding company, Jiangsu Changjiang Electronics Technology Co., Ltd (‘JCET’) has appointed Dr. Lee Choon Heung as Chief Executive Officer (‘CEO’) for JCET Group, as well as Chief Executive Officer and Chairman for STATS ChipPAC.
Dr. Lee brings to JCET a wealth of expertise and veteran leadership with 20 years of extensive semiconductor packaging and test experience. Dr. Lee served in several senior management positions at Amkor Technology Inc. including head of their R&D centre, head of global procurement, group vice president, senior vice president and Chief Technology Officer. Dr. Lee, holds a Ph.D. in Theoretical Solid State Physics from Case Western Reserve University, currently holds 59 industry patents, and has published 19 academic papers around the world.
“We are excited about the opportunity to bring on board an industry leader of the calibre of Dr. Lee Choon Heung as our new JCET Group CEO” stated JCET Chairman, Mr. Wang Xinchao. “We are confident in his ability to lead JCET as we continue our growth in both technology and scale moving forward,” continued Mr. Wang. Mr. Wang will continue in his role as Chairman of JCET Group.
The JCET Board of Directors and the management team also expressed their utmost gratitude and appreciation to Dr. Han Byung Joon and Mr. Lai Chih-Ming for their outstanding leadership and valuable contributions during their tenure at STATS ChipPAC. Dr. Han is resigning as chairman of the board of STATS ChipPAC. Mr. Lai will now serve in a new role as executive vice president of JCET Group.
Certain of the statements in this release, including statements regarding the Company’s intellectual property, are forward-looking statements that are based on management’s current views and assumptions and involve a number of risks and uncertainties which could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; shortages in supply of key components and disruption in supply chains; disruption of our operations and other difficulties related to the relocation of our China operations; loss of directors, key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; beneficial ownership by Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) of all of our ordinary shares that may result in conflicting interests with other holders of our securities; our inability to capture all or any of the benefits from acquisitions and investments in other companies and businesses or from the acquisition of us in August 2015 by JCET-SC (Singapore) Pte, Ltd., which is now wholly-owned by JCET; loss of customers or failure to compete effectively with our former Taiwan subsidiaries which we have divested in 2015; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; and other risks. All our forward looking statements are expressly qualified in their entirety by the cautionary statements set forth above. You should not unduly rely on such forward-looking statements, which speak only as of the date of this release. STATS ChipPAC does not intend, and does not assume any obligation to update any industry information or forward-looking statements to reflect subsequent events or circumstances. In light of these risks, uncertainties and assumptions, any of the events anticipated in these forward-looking statements might not occur.
About STATS ChipPAC Pte. Ltd.
STATS ChipPAC Pte. Ltd. is a leading service provider of semiconductor packaging design and characterization, wafer bump, assembly and test solutions for diverse end market applications in communications, digital consumer, computing and automotive electronics. Headquartered in Singapore, STATS ChipPAC has design, research and development, manufacturing and customer support offices throughout Asia, the United States and Europe. STATS ChipPAC is a member of the JCET Group of companies. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.
Founded in 1972, Jiangsu Changjiang Electronics Technology Co., Ltd. (“JCET”) is one of the top semiconductor packaging and test providers in the world and the largest provider in China. With full turnkey services encompassing design and characterization, wafer bump, packaging and test, JCET is a strategic partner for semiconductor companies across a broad range of markets and applications. The comprehensive packaging portfolio of JCET and its subsidiaries include discrete, leaded, laminate, flip chip, Molded Interconnect System, wafer level packaging and System-in-Package technologies. Headquartered in Jiangyin, Jiangsu, China, JCET has an extensive global manufacturing base with operations in China, Singapore and South Korea. JCET is a publicly-traded company that is listed on the Shanghai Stock Exchange. Further information is available at www.jcetglobal.com.