STATS ChipPAC is a leading provider of advanced semiconductor packaging and test services to global customers in the communication, consumer and computing markets. With a broad technology portfolio ranging from leadframe and laminate packages to advanced fan-out and fan-in wafer level technology, flip chip interconnect, System-in-Package (SiP), Through Silicon Via (TSV) and 2.5D/3D packaging, STATS ChipPAC provides customers with innovative and cost-effective semiconductor solutions. STATS ChipPAC differentiates itself through innovative packaging solutions in embedded Wafer Level Ball Grid Array (eWLB), encapsulated Wafer Level Chip Scale Packaging (eWLCSP) and fcCuBE® technology as well as our breakthrough wafer level manufacturing method known as FlexLineTM.
Founded in Singapore in 1994, STATS ChipPAC grew successfully over the years into a global Outsourced Semiconductor Assembly and Test (OSAT) provider with strategic manufacturing operations in Singapore, South Korea and China. These sites are integrated with our global network of research and development, design and customer support offices throughout Asia, the United States and Europe.
STATS ChipPAC was acquired in 2015 by JCET-SC (Singapore) Pte. Ltd. (“JCET-SC”). JCET-SC is beneficially owned by China Integrated Circuit Industry Investment Fund Co., Ltd., Siltech Semiconductor (Shanghai) Co., Ltd. and Jiangsu Changjiang Electronics Technology Co., Ltd. (JCET). Founded in 1972, JCET is the largest semiconductor packaging and test provider in China. JCET’s product portfolio covers leaded, discrete, laminate, bumping and wafer level chip scale packaging (WLCSP). Headquartered in Jiangyin, Jiangsu, China, JCET has four manufacturing facilities in the Jiangsu and Anhui provinces in China. JCET is a publicly-traded company that is listed on the Shanghai Stock Exchange.
Jiangyin Changdian Advanced Packaging Co., Ltd. (JCAP) is a subsidiary of JCET which provides turnkey services including wafer bump, probe and assembly. Founded in August 2003, JCAP is a leader in advanced wafer bump technology (solder bump, gold bump, pillar bump) and Wafer Level Chip Scale Packaging. JCAP’s facilities are located in Jiangyin, Jiangsu, China.
As a member of the JCET group of companies, STATS ChipPAC has the competitive advantage of increased manufacturing scale with a combined product portfolio ranging from discrete and low leadcount devices to the most advanced flip chip, wafer level, SiP and 2.5D/3D packaging solutions.
- Customer-centric designers
- Mobile design capability
- State-of-the-art design tools
- Integration of customer supplied designs into STATS ChipPAC’s design system
- Project data management
- Flip Chip Packaging
- Wafer Level Packaging
- Re-Passivation and Redistribution Layer (RDL)
- Cantilever probing up to 32 test sites in parallel
- Vertical probing up to 32 test sites in parallel
- 2 and 3 row staggered probing
- Sampled probing to lower the costs of Wafer Sort
- Probe card design, development and maintenance
- Flip Chip Packages
- MEMS and Sensors
- System-in-Package (SiP)
- Wafer Level Packages (WLP)
- Wirebond Packages
- Test Facilities
- Test Platforms
- Wafer Sort
- Test Development Services
- RF Test
- Mixed Signal Test
- and more…
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