Fine Pitch Land Grid Array (FLGA)

FLGASTATS ChipPAC’s FLGA is a laminate substrate based package with plastic overmolded encapsulation. Unlike a standard FBGA, second level interconnect is achieved on the LGA by connecting "lands" on the package directly onto the PCB through solder re-flow. The elimination of solder balls brings better electrical performance and lower package profile without using the more expensive thinner BT core material. It also offers the flexibility of land pattern arrangement in the form of signal lands or heat spreader/ground pads to suit the thermal and electrical requirements of various devices. The FLGA package’s reduced outline and thickness make it an ideal advanced technology packaging solution for high performance and/or portable applications. STATS ChipPAC’s FLGA is available in a broad range of JEDEC standard body sizes including TFLGA (<1.20mm), VFLGA (<1.00mm), WFLGA (<0.80mm) UFLGA (<0.65mm) package thickness.

FLGA is also available in a stacked version.Stacked Die Land Grid Array (FLGA-SD) is available in 1.2mm (TFLGA-SD), 1.0mm (VFLGA-SD), 0.8mm (WFLGA-SD), 0.65mm (UFLGA-SD) and 0.5mm (XFLGA-SD) maximum thickness. STATS ChipPAC’s chip stack technology offers the flexibility of stacking 2 to 8 die in a single package. Die to die bonding capability enables device and signal integration to improve electrical performance and reduce overall package I/O requirements. Wafer thinning technology, overhang wire bond technology, and the use of spacers between stacked die provide the flexibility to stack almost any desirable configuration of die in one package. This capability uses existing assembly infrastructure, which results in more functional integration with lower overall package cost. The use of the latest packaging materials allows this package to meet JEDEC Moisture Resistance Test Level 2a with Lead-free reflow condition. This is an ideal package for cell phone applications where Digital, Flash, SRAM, PSRAM and Logic are stacked into a single package.

Features (general)

  • Low profile
  • Flexible body sizes range from 4 x 4mm to 13 x 13mm; up to 12mmx18mm for stacked versions)
  • Flip chip and discrete passive options (SiP)
  • Minimum 0.50mm pitch (array and peripheral land pads)
  • Flexible land pattern arrangement
  • Pb-free and halogen-free compatible materials available
  • JEDEC standard compliant

Features (stacked versions)

  • 2 to 8 die stack with spacer capability
  • Flexible die stacking options ("pyramid," "same die," etc.)
  • Memory, Logic, Analog and RF combinations
  • Package height at 0.5, 0.65, 0.80, 1.0, 1.2, 1.4mm max
  • Die thinning to 40um (1.6mils) capability
  • Low loop wire bonding; reverse and die to die
  • Up to 2mm die overhang per side
  • Film spacer capability for decreased die stack thickness
  • Very thin substrate capability
  • Capability to integrate discrete passives or integrated passive devices
  • Halogen-free and Low-K wafer compatible BOM

End Applications

  • Handheld devices
  • Wireless RF
  • Analog
  • ASIC
  • Memory
  • Simple PLDs


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