Thermal Characterization

Thermal Characterization

STATS ChipPAC offers thermal simulation services to predict the junction temperature and thermal resistance of integrated circuit (IC) packages.  Thermal simulations optimize the thermal performance of IC packages to meet a customers’ requirements or specifications. 

Thermal Performance Simulation per JEDEC or Customer's Conditions

All ICs generate heat when power is applied to them. Thermal management should be considered during package selection to ensure high product reliability. Therefore, to maintain the device's junction temperature below the maximum allowed, effective heat flow from the IC through the package to the ambient is essential. STATS ChipPAC offers the simulation of thermal resistance of an IC package. Thermal resistance measures the package's ability to transfer heat generated by the die to the circuit board or the ambient. By calculating the temperatures at two points, the amount of heat flow from one point to the other is determined by the thermal resistance. By knowing the thermal resistance of a package, the IC's junction temperature can be calculated for a given power dissipation and its reference temperature. STATS ChipPAC offers thermal simulation using JEDEC test conditions, including Theta JA, Theta JC, Theta JB, Psi JT, and Psi JB. 

STATS ChipPAC also offers Simplified Package Modeling (SPM) which is the simplest model to calculate the system level thermal simulation for customers.  The SPM has very high accuracy (less than ~5% of error) compared to a detailed modelling approach.


Optimization of Materials and IC Configurations

In addition to satisfying the JEDEC test conditions, STATS ChipPAC optimizes the materials and configurations of IC packages in order to meet special thermal requirements.  STATS ChipPAC’s research and development engineers work closely with customers to optimize the critical thermal factors to improve thermal performance.