Flip Chip PoP (Bare Die)

Bare Die Flip Chip Package-on-Package (fcPoP)

STATS ChipPAC’s Package-on-Package (PoP) family includes a stackable flip chip BGA as the bottom PoP package (PoPb). PoPb is typically an application processor or a baseband device with land pads placed on the top periphery of the package surface to enable the stacking of a second FBGA or PoP top (PoPt) above. PoPt, with memory devices stacked within, is assembled, tested and yielded independently. The two packages are combined by reflowing together (usually performed simultaneously) on the application board to form PoP (Z-interconnection with solder ball).


PoP has emerged as the preferred approach to integrate memory and logic in many advanced mobile and handheld applications. The bottom logic package and top memory package can be assembled, tested and yielded independently. This business model is preferred by end users as they can leverage their usual suppliers for these device types independently and have the flexibility to match logic processor and memory to support different applications.

STATS ChipPAC has always been at the forefront of 3D packaging and stacked die packaging. The wire bonded bottom PoP package was developed and introduced into production years ago. The bottom fcPoP provides the advantage of denser design with larger die size and higher number of IOs within the same PoP package body size / form factor as compared to the wire bonded PoP version. In addition, the use of fcPoP allows for potentially lower PoPb package height, thus reducing the total package stacked height post-SMT process. Improved device electrical performance can also be expected with the fcPoP package as with all other Flip Chip packages in comparison to wire bonded designs. Bare die fcPoP package offers the lowest cost PoP package type and can use down to 0.4mm memory interface (MI) pitch.


  • Stacking fully tested memory and logic packages eliminates known good die (KGD) issues
  • Package-on-package stacking provides flexibility in mixing and matching IC technologies
  • Devices can be procured from multiple manufacturing sources
  • Meets accepted package and board level reliability standards for CSP
  • Flip chip enables higher performance, higher density, finer top PoP ball pitch and a smaller/thinner PoP solution
  • CuOSP or Ni/Au on bottom pads of bottom PoP (PoPb) with lead-free ball options
  • Ni/Au on top memory interface pads of PoPb
  • Die thickness down to 70µm proven
  • Supports 0.4mm minimum ball pitch on bottom/BGA pads and as low as 0.4mm pitch on top memory interface pads of PoPb
  • Capable process with 45nm and 28nm FAB technology in both lead-free and eutectic flip chip bumps
  • Advanced UF process maximizes allowable die size in package, with 35µm chip gap height 
  • Bottom PoP package thickness of 0.7mm max with 70µm thick flip chip die and 4 layer BU substrate
  • Optimization of materials to meet warpage requirements during surface mount process
  • Full in-house electrical, thermal and mechanical simulation and measurement capability
  • Full in-house package and substrate design capability
  • Turnkey solution including wafer bumping in both eutectic SnPb and lead-free solder


  • PoPb: Application, baseband or multimedia processor for mobile handset and portable devices
  • PoPt: Memory to support system and processor functions including DDR, Flash (NAND, NOR), SRAM and combinations thereof


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