WLCSP (FIWLP Technology)

Wafer Level Chip Scale Package (WLCSP)

STATS ChipPAC offers high performance fan-in wafer level packaging (FIWLP) solutions that provide significant package footprint reductions, lower cost, improved electrical performance, and a relatively simpler construction over conventional wirebond or interposer packaging.

The WLCSP Advantage

  • 200mm & 300mm wafer bumping offers advanced technology in WLP services that enable higher current densities & increased reliability
  • Repassivation, Redistribution, Bumping and IPD layer options available
  • Full turnkey wafer bumping & Flip Chip-in-Package assembly capability

Wafer Level Chip Scale Package (WLCSP) offers one of the most compact package footprints, providing increased functionality, improved thermal performance and finer pitch interconnection to the printed circuit board. Based on its small form factor and low cost, WLCSP has experienced significant growth driven aggressively by mobile consumer products because of the small form factor and high performance requirements. With WLCSP, all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual chips to achieve a package that is essentially the same size as the die. The resultant package has dielectrics, thin film metals, and solder bumps directly on the surface of the die with no additional packaging. The basic structure of the WLCSP has an active surface with polymer coatings and bumps with bare silicon exposed on the remaining sides and back of the die. The WLCSP is the smallest possible package size since the final package is no larger than the required circuit area.

Breakthrough FlexLine™ Wafer Level Manufacturing

STATS ChipPAC’s innovative approach to WLCSP manufacturing, known as the FlexLine™ method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow.  This FlexLine™ manufacturing method is a significant paradigm shift from conventional wafer level manufacturing, and delivers an unmatched level of flexibility and cost savings for wafer level packaging including WLCSP.
FlexLine Process Flow

By normalizing multiple wafer diameters to a uniform processing size through reconstitution, incoming wafer diameters become irrelevant as this no longer dictates manufacturing capacity or limits process capabilities. When 200mm wafers are reconstituted into 300mm or larger panel sizes, customers have greater potential for cost reduction than conventional WLP manufacturing. As panel size increases, the cost of producing wafer level packages drops significantly when compared to conventional WLP methods. As a result, FlexLine™ can help our customers achieve at least a 15-30% cost reduction using the optimum design requirements for their WLCSP devices.

Superior Quality, Lower Costs: eWLCSP™

eWLCSP The encapsulation material that is a part of the FlexLine manufacturing process has enabled an innovative WLCSP packaging technology called encapsulated Wafer Level Chip Scale Package (eWLCSP™). An intrinsic feature of eWLCSP™ is the thin polymer casing formed on the back and four sidewalls of the die, providing mechanical robustness and resistance to chipping, cracking and handling damage, as well as improved long term reliability compared to traditional bare die WLCSP. eWLCSP provides a measurable increase in overall component strength of more than 50% over traditional WLCSP structures. The combined benefits of superior quality, lower cost structure and the ease of conversion through a drop-in replacement make eWLCSP™ a compelling value proposition.

WLCSP Features

  • WLCSP body sizes qualified up to 6x6mm
  • Ball count ranges depending on pitch size and up to 300
  • Die services available for 8”-12” wafers
  • In-house thin film on wafer processing & bumping
  • Full service wafer bumping with Polyimide or PBO dielectric options for wafer repassivation, redistribution and IPD layers
  • Bumps formed by printed paste, electroplate or ball drop solder bump technologies
  • Minimum available flip chip bump pitch of 150µm
  • Large bump (220-500µm) processing at 0.35mm pitch & greater for Flip Chip-on-Board & WLCSP applications
  • For larger pitch applications, either printed paste bumping or mechanical ball drop available
  • Eutectic and Pb-free solder
  • Copper under bump metallization (UBM) & redistribution layers (RDL) available
  • Wafer level IPD & thick copper (8-12µm) conductors available
  • Underfilling of substrate mounted bumped die may or may not be required depending on customer’s specific application & reliability requirements
  • Underfilling by overmolding is feasible
  • Low cure temperature polymers available
  • Flexible bare die processing
  • Compatible with conventional SMT assembly and test techniques

WLCSP Market Applications & Drivers

A small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications and other portable consumer and industrial devices.