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Through Silicon Via (TSV)
Through Silicon Via (TSV)
Enabling 2.5/3D package for low power, high performance devices in the mobile, wireless connectivity and networking markets
Key requirement in the convergence of mobile communication and computing functionality in devices such as smartphones and tablets
Higher interconnect density and greater space efficiencies compared with traditional wirebonding and flip chip stacking by means of face-to-back and face-to-face bonding
A Pioneer in TSV Technology
As a longstanding leader in 3D packaging, STATS ChipPAC was one of the first OSAT providers to invest in back-end of line (BEOL) manufacturing capabilities for 2.5D and 3D TSV technology, opening a 51,000 sq. ft. R&D facility in Woodlands, Singapore dedicated to the development of next-generation wafer-level integration with TSV technology. STATS ChipPAC’s BEOL services include chip-to-chip and chip-to-wafer assembly with stealth dicing and fine pitch micro-bump bonding down to 40um.
STATS ChipPAC’s TSV capabilities also include 300mm mid-end of line (MEOL) processing capabilities in areas such as TSV formation and metallization, bumped wafer thinning, thin wafer handling, 3D microbump bonding, wafer-level underfill and TSV assembly. State of the art process equipment and metrology tools were installed and qualified as part of a high volume manufacturing expansion of 300mm wafer capability, bringing TSV into volume production mode. Additional expansion in 2012 is further increasing volume and quality levels of all advanced wafer scale products including TSV.
TSV is an important developing technology that utilises short, vertical electrical connections or “vias” that pass through a silicon wafer in order to establish an electrical connection from the active side to the backside of the die, thus providing the shortest interconnect path and creating an avenue for the ultimate in 3D integration. TSV technology offers greater space efficiencies and higher interconnect densities than wire bonding and flip chip stacking. When combined with microbump bonding and advanced flip chip technology, TSV technology enables a higher level of functional integration and performance in a smaller form factor.
STATS ChipPAC TSV Capabilities
TSV Mid-End Process (MEOL)
Bumped wafer thinning and planarization
Backside via reveal
Silicon recess and backside metallization
Thin wafer with TSV handling and dicing
Microbump technology for 50/40um u-bump plating
Capability to handle 28nm silicon node and below
TSV Assembly/Packaging (BEOL)
Chip-to-Wafer or Chip-to-Chip attachment options
Fine pitch microbump bonding and stealth dicing down to 40um (solder, Cu column)
Wafer level underfill (ultra-small gap underfill process)
TSV package reliability & characterization
Developing Next-Generation 2.5/3D TSV packaging
TSV Silicon Interposer Technology
First step for TSV integration
Qualified tapered TSV process for low density Si interposer (sub-200um pitch)
High density Si Interposer with TSV in joint development
Potential to replace high-end organic (BU) substrates
Thinner profile, tighter pitch and high thermal/electrical performance
TSV Assembly / Packaging (BEOL)
STATS ChipPAC has full front- to back-end manufacturing capabilities for 200mm wafers and currently handles both chip-to-chip (C2C) and chip-to-wafer (C2W) assembly for TSV technology. This includes high density microbump capabilities in both solder and copper column, microbump bonding down to 40um pitch, thin wafer handling, wafer-level underfill, thin wafer dicing and microbumps for flip chip interconnection. Microbump technology is critical to delivering fine pitch, low profile solutions for high performance devices.
TSV Assembly Packaging Options
TSV Mid-end Fabrication (MEOL)
STATS ChipPAC offers a post-TSV “mid-end” fabrication process flow that occurs between the wafer fabrication and back-end assembly process. Mid-end processes support the advanced manufacturing requirements of 2.5D and 3D TSV, as well as wafer-level packaging, flip chip and embedded die technology. The mid-end process includes temporary bonding/de-bonding, wafer thinning and planarization, back-side via reveal, silicon recess and back-side metallization and microbumping. Microbump is required to meet fine pitch, low profile applications in 3D TSV, stacking and assembly. STATS ChipPAC offers 60/40um pitch microbump bonding.
TSV Interposer and Assembly
STATS ChipPAC offers TSV interposer fabrication to provide a “bridge” between today’s 2D packaging solutions and next-generation 3D technology. Often referred to as 2.5D technology, TSV interposers are an efficient and practical approach to die level integration. TSV interposers provide flexibility for the integration of die from different technology nodes and deliver advantages in miniaturization, thermal performance and fine line/width spacing in a semiconductor package.
TSV Technology Integration
STATS ChipPAC is incorporating Through Silicon Via (TSV) and Integrated Passive Devices (IPD) technologies with embedded Wafer Level Ball Grid Array (eWLB) technology in advanced 2.5D and 3D designs to effectively address heterogeneous technology integration where mixed die sizes and silicon lithography nodes are combined into thin package profiles to meet enhanced flexibility, functionality and form factor objectives.
TSV in IPD
Adding TSV to the IPD structure results in a unique high functionality solution
Performance and margin improvements result from increased distance between IPD surface and ground plane
TSV Fact Sheet
eWLB (FOWLP) datasheet
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STATS ChipPAC Ltd. is a leading service provider of advanced semiconductor packaging design, assembly, test and distribution solutions.
A trusted partner and supplier to leading semiconductor companies worldwide, STATS ChipPAC provides fully integrated,
multi-site, end-to-end packaging and testing solutions that bring products to the market faster.
© 2015 STATS ChipPAC Ltd.