embedded Wafer Level Ball Grid Array

Demand for wafer level packaging is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. Embedded Wafer Level Ball Grid Array (eWLB) technology was developed to provide a wafer level packaging solution for semiconductor devices requiring a higher integration level and a greater number of external contacts. eWLB technology uses a combination of traditional ‘front-end’ and ‘back-end’ semiconductor manufacturing techniques which greatly reduces manufacturing costs while providing a smaller package footprint with higher input / output (I/O) along with increased thermal and electrical performance.

eWLB technology is an enhancement of standard wafer level packages (WLPs) and is successfully enabling semiconductor manufacturers to provide the smallest possible, highest performing semiconductor package technology. Backed by a strong infrastructure and cost effective manufacturing process, STATS ChipPAC offers a high performance solution at a lower cost point with volume and maturity, leveraging the potential of batch panel processing of high density wafer fabrication redistribution technology. STATS ChipPAC has established a robust eWLB high volume manufacturing process with automated wafer reconstitution (including wafer level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 8” and 12” diameters can be supported, and no bumping is required as the package is essentially built on top of a reconstituted wafer.

eWLB is a Fan-Out WLP (FO-WLP) as opposed to a more conventional Fan-In WLP (FI-WLP). The advantage is that the eWLB package size is decoupled from the die size, unlike FI-WLP. This allows for ball pitch and I/O count not to be limited by the die size. Thus, die shrinks can be accommodated and larger ball pitches that would not fit within the die area of a FI-WLP can be supported . Due to use of special materials, the package size and ball count of eWLB can be extended beyond that of FI-WLP and still meet board level reliability requirements. This allows for a broader application range for the eWLB to larger size and ball count mobile and consumer devices, while still giving the advantages of WLP related to performance, simple logistics and supply chain, lead free/halogen free and compatibility with advanced wafer fabrication nodes.

eWLB Features

• Combines traditional front-end and back-end manufacturing techniques with parallel processing of all chips on the wafer
• Batch processing increases throughput and reduces manufacturing costs
• Elimination of substrate simplifies supply chain and reduces cost
• Provides the performance of fan-in WLP but decouples die from package size for greater flexibility
• Enables a dramatically higher number of external contacts as compared to fan-in WLP
• No substrate required
• Miniaturized high performance package
• Green packaging (Pb-free and Halogen-free)
• Cu/low-k (ELK) compatible packaging technology
• Batch process of wafer level including wafer level test
• Embeds die in mold during assembly/packaging
• Supports incoming wafers in both 8” and 12” diameters
• No bumping required
• Low packaging and test costs due to batch process
• Excellent electrical and thermal performance
• Simple logistics and supply chain (no substrate, bumping, etc.)

Applications

Typical applications for eWLB are baseband, RF, power management, analog and other emerging applications primarily for mobile and consumer products.

Next Generation eWLB

While the first generation of eWLB technology is designed for single metal RDL on the bottom side of the eWLB package, the next generation of eWLB technology focuses on two metal-layer RDL, multiple die side-by-side to support System-in-Package (SiP), and extension of package size to 12x12mm with thinner overall thickness. Vias through the package are also envisioned to extend the eWLB package into the 3D SiP application space. STATS ChipPAC is working with technology partners to extend the capability of the eWLB package platform, providing more integration capability, value and performance.

eWLB Process Flow

1)	Reconstituted wafer
	•	Wafer saw and pick-and-place from incoming wafer
	•	Probed good die
	•	Molded reconstituted wafer using proven materials
	•	Molded artificial wafer starting point for thin film technology
2)	Redistribution
	•	Thin film technology with advanced design rules
	•	Standard thin film equipment
	•	Proven and reliable material set
3)	Ball Mount and Singulation
	•	Standard back-end assembly flow (and equipment)
4)	Test, Mark, Scan, Pack
	•	Standard or wafer level-based test flow
	•	Standard assembly

 

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