Wafer Level Technology

Wafer Level Technology

wafer level packaging Wafer Level Technology Options

STATS ChipPAC offers wafer level processing technologies for the following package options:

  • SiP (System-in-Package)
  • eWLB (embedded Wafer Level Ball Grid Array)
  • WLCSP (Wafer Level Chip Scale Packages)
  • eWLCSP™ (encapsulated Wafer Level Chip Scale Packages)
  • Through Silicon Via (TSV)
  • IPD (Integrated Passive Devices)

    Today's consumers are looking for sophisticated mobile devices that can handle a wide range of functions and applications in a single, small end-product. This mobile technology convergence is pushing traditional packaging well beyond typical limits in the areas of form factor, reliability and performance, evolving from substrate-based package configurations to more complex wafer level packaging. STATS ChipPAC is an industry leader in providing a comprehensive platform of wafer level technology solutions that include Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP) and Integrated Passive Devices.

    Breakthrough FlexLine™ Wafer Level Manufacturing



    STATS ChipPAC’s innovative approach to WLCSP manufacturing, known as the FlexLine™ method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow.  This FlexLine™ manufacturing method is a significant paradigm shift from conventional wafer level manufacturing, and delivers an unmatched level of flexibility and cost savings for both Fan-In and Fan-Out wafer level packaging.

    FlexLine Process Flow

    Fan-In WLP or Wafer Level Chip Scale Packages (WLCSP)

    As a small, lightweight, high performance semiconductor solution, WLCSP is a FIWLP technology that offers compelling packaging solutions for cost and space constrained applications. Advantages of WLSP include:
    • A true Chip Scale Packaging (CSP) technology where the package is the same size as the die
    • Advanced wafer level process such as low cure temperature polymers and the use of copper for under bump metalization (UBM) and redistribution layers (RDL) to achieve higher densities and increased package reliabilities

    Superior Quality, Lower Costs: eWLCSP™

    Utilizing the FlexLine™ manufacturing approach, STATS ChipPAC has developed an innovative packaging technology called encapsulated Wafer Level Chip Scale Package (eWLCSP™). eWLCSP™ offers significant structural advantages over traditional WLCSP designs. As a bare die package, WLCSP is regularly exposed to potential cracking, chipping and handling issues that can occur before or during the SMT assembly process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile. eWLCSP™ is equivalent to a conventional WLCSP product with the addition of a thin protective coating on the backside and four sidewalls of the die, achieving increased durability and reliability within the standard WLCSP size specification.

    Encapsulation offers a variety of advantages:
    • Mechanical protection from die chipping, cracking and other handling issues
    • Optical protection where needed
    • Safeguards the silicon during socket insertion for test
    • Higher quality due to significant increase in component break strengths


    In addition, eWLCSP electrical performance is equivalent to WLCSP with proven results in component level reliability (CLR), temperature cycle on board (TCoB) and drop test. A product currently using a conventional WLCSP process can be converted to eWLCSP without any silicon design change required, regardless of the current silicon wafer diameter. The FlexLine method can reduce WLCSP costs by 15-30% when using the optimum design requirements for WLCSP devices. For example, using the FlexLine method, 200mm incoming wafers can be reconstituted into 300mm or larger panel sizes, providing customers with the advantage of panel size scaling--with further per-unit cost reductions as panel sizes increase.

    Fan-out WLP or embedded Wafer Level Ball Grid Array (eWLB)

    For applications requiring small packages with significantly higher I/O, STATS ChipPAC offers a proven technology called eWLB. eWLB is a powerful FOWLP technology that has the design flexibility to accommodate an unlimited number of interconnects and is unconstrained by die size. This enables eWLB to deliver maximium connection density, improved electrical and thermal performance and smaller package dimensions to meet the relentless form factor and performance requirements of the mobile market. STATS ChipPAC is an industry leader in eWLB technology, providing innovative package designs and an efficient manufacturing process that is well-suited for a multitude of complex and highly integrated solutions.

    Integrated Passive Devices (IPD)

    Passive devices such as resistors, capacitors, inductors, filters and baluns can consume 60-70% of available space in a system, subsystem or System-in-Package (SiP). As one of the first companies in the industry to integrate and fabricate passive devices at the silicon wafer level, STATS ChipPAC is able to produce IPDs which are significantly smaller, thinner and higher performing than standard discrete passive devices that are commercially available today. STATS ChipPAC can embed IPDs in very close proximity to the active die in packages, providing significant performance, size reduction and flexible device integration capabilities.

    Versatile technology platform for 2.5D and 3D integration

    Increasing demand for more advanced, smaller and lighter mobile products with superior functionality and lower overall cost is driving the need for more innovative and sophisticated packaging technologies. eWLB technology provides a versatile platform for the semiconductor industry's evolution from single or multi-die 2D packages to 2.5D and 3D ICs or SiP configurations that deliver:
    • Higher performance
    • Higher frequencies
    • Higher bandwidth
    • Thinner package profiles

    Full Turnkey Wafer Level Services at STATS ChipPAC

    With our unmatched strength in wafer bump, test and die level services, STATS ChipPAC is uniquely positioned to provide full turnkey wafer processing to our customers. We can lower both cost and cycle time by offering a broad spectrum of wafer bumping related processes, including:
    • Wafer bumping and redistribution services
    • Full turnkey services for embedded Wafer Level Ball Grid Array (eWLB) applications
    • Full turnkey services for advanced Flip Chip applications
    • Full turnkey services for Wafer Level Chip Scale Packages (WLCSP)

       

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