Flip Chip

Low Cost Flip Chip (LCFC)

STATS ChipPAC’s Low Cost Flip Chip (LCFC) packages form a subgroup in the Flip Chip package family which represents any flip chip platforms that leverage cost saving features such as nSOP (no Solder on Pad), MUF (mold underfill) and BOL (bond on lead) interconnection to name a few.

LCFC packages are produced on substrates with matrix strip or singulated format, and use overmolding and saw singulation processes for strip base substrate similar to wire bond packages of the same form factor. The fcBGA is typically an exposed die package with CUF (capillary underfill); fcFBGA is typically an overmolded package; both fcBGA and fcFBGA use solder balls for second level (BGA) interconnection; fcFBGA-SDx represents a variation of fcFBGA comprising a “hybrid” stacked construction, i.e., flip chip die on the bottom and wire bond die on the top; while the fcLGA is an exposed die product that does not have solder balls.

STATS ChipPAC’s LCFC packages are available in ball counts ranging from 32 to > 1000 depending on body size and external terminal (BGA) pitch. Other features such as heat spreaders for thermal enhancement, surface mounted passive components, etc. that are offered with traditional fcFBGA and fcBGA packages are also available for LCFC packages.

Flip Chip interconnection provides the ultimate in miniaturization and reduced package parasitics and enables new paradigms in the area of power and ground distribution to the chip which are not feasible with traditional wire bond packaging. STATS ChipPAC offers full turnkey services ranging from design through production, including high speed, high pin count digital and RF testing.

Features

  • Routing-efficient interconnection structure & optimized bump layout help “fit” flip chip designs into low cost laminate substrates
  • Mold underfill (MUF) process technology
  • Elimination of Solder-on-Pad (SOP) process on substrates
  • Mechanics of interconnect structure eliminates ELK/ULK damage on advanced Si node devices despite use of Cu column (Pb-free) bump metallurgy & dense routing
  • Scalability to high I/O density & fine pitch, Pb-free electromigration without burden on sub-design rules
  • High throughput processing through combination of high UPH unit processes, optimization of material flow & equipment selection
  • High density matrix strip for fcFBGA & wide boat format for singulated substrate handling for fcBGA
  • Smaller package size & lower electrical parasitics achievable compared with corresponding wire bond package options
  • LCFC package cost below wire bond package cost
  • Applicable across full range of fcBGA & fcFBGA package families
  • Sn-Pb, Sn-Ag (Pb-free) and Cu column bumps
  • Bumped wafer thinning: 100µm Si thickness in production, 75µm qualified
  • Conventional 2/4 layer laminate, laminate Build-up (BU) & ABF BU substrates
  • 150µm bump pitch in production, 80µm in development with Cu column bump
  • 0.40mm minimum package ball (BGA) pitch in production
  • Package body sizes ranging from 4 x 4mm through 45 x 45mm
  • In-house wafer bumping with plated & printed bumps for 200 & 300mm wafers
  • Mold underfill (MUF) with solder bump in production, qualified with Cu column bump

End Applications

Devices primarily for wireless and portable products such as RFICs and power/analog ICs driven by miniaturization and low package parasitics, and for ASIC, graphics and computing products driven by superior electrical and thermal performance.