Flip Chip

Flip Chip Chip Scale Packages (fcFBGA / fcCSP)



STATS ChipPAC’s fcLFBGA and fcLGA packages form a subgroup in the Flip Chip package family which represents the form factor popularly known in the industry as CSP (Chip Scale Package). The fcLFBGA, fcTFBGA-SD2 and fcLGA are produced on substrates with matrix strip format and use overmolding and saw singulation processes similar to wire bond packages of the same form factors. The fcLFBGA is an overmolded package with solder balls and fcTFBGA-SD2 is an overmolded hybrid product (flip chip on the bottom and wire bond die on the top), while the fcLGA is an exposed die product that does not have solder balls. STATS ChipPAC’s Flip Chip FBGA packages are available in ball counts ranging from 32 to 900, body sizes from 5 x 5mm to 15 x 15mm and various package formats. Flip Chip interconnection provides the ultimate in miniaturization, reduced package parasitics and enables new paradigms in the area of power and ground distribution to the chip which are not feasible with other traditional packaging approaches. STATS ChipPAC offers full turnkey services ranging from design through production, including high speed, high pin count digital and RF testing.


Features

  • Eutectic SnPb, hi-Pb or Pb-free bumps
  • Minimum overall height of 1.40mm for fcLFBGA; 1.20mm for fcTFBGA; 1.00mm for fcVFBGA; 0.65mm for fcLGA
  • Conventional 2 and 4 layer through-hole or PPG build-up laminate substrates available
  • ABF build-up substrates available
  • 150µm minimum die bump pitch in production
  • 0.40mm minimum package ball (BGA) or pad (LGA) pitch in production
  • Body sizes 4 x 4mm through 15 x 15mm using matrix strip format
  • In-house wafer bumping with plated and printed bumps for 6, 8 and 12 inch wafers including BCB and polyimide re-passivation and RDL option
  • Molded underfill (MUF) with solder bump in production; MUF with Cu column bump qualified
  • High density wide strip available

End Applications

Devices for wireless and portable products such as microprocessors, RFICs and power/analog ICs driven by miniaturization and low package parasitics.