Flip Chip

Flip Chip Ball Grid Array (fcBGA)

STATS ChipPAC’s high-end BGA Flip Chip packages include the fcBGA, fcBGA-SiP, fcBGA-H, fcBGA-MP and fcBGA-SS2/SS3. The fcBGA package is the main platform in this package sub-group, which also includes a thermally enhanced version with heat spreader (fcBGA-H) and a package subsystem meeting the standard BGA footprint that contains multiple components within the same package (fcBGA-MP).

STATS ChipPAC’s Flip Chip BGA packages are available in ball counts ranging from 220 to 3213, body sizes from 12 x 12mm to 55 x 55mm and various package formats.

Flip Chip interconnection provides the ultimate in miniaturization, reduced package parasitics and enables new paradigms in the area of power and ground distribution to the chip which are not feasible with other traditional packaging approaches. STATS ChipPAC offers full turnkey services ranging from design through production, including high speed, high pin count digital and RF testing.


  • High performance packages up to 55mm body size with >3213 pins, and thermal solutions ranging from bare die, stiffener only, and one/two piece heat spreader
  • ABF buildup to 6-2-6, minimum core thickness down to 200um; coreless substrate and grounded lid for high electrical performance
  • Packaging solution for Eu/LF bumped 28N/32N node with Extra/Ultra low K die-electric
  • “Green” flip chip solution with Pb-free, Cu-column bump and halogen-free material sets
  • 65N/Low K, 40N/ELK, & 28/32N ELK/ULK
  • Eutectic, high Pb, Pb-free and Cu-column bumps
  • Nitride, Polyimide, PBO wafer passivations
  • Ni-Au, Ni-Pd-Au, SOP (solder-on-pad), OSP (organic solderable preservative), Ni-free SOP pad & immersion Sn finish
  • Bumped wafer thinning down to 100µm for non-molded fcBGA 
  • 200mm (printed, plated) & 300mm (plated) bumped wafers; RDL with 200mm & 300mm bumped wafers
  • Seamless integration of flip chip, SMT and in-line open/short testing operations
  • F/A metrology tools for rapid diagnostics and debugging, including TDR, CSAM, X-ray, Ion milling and SEM
  • All packages qualified to JEDEC specifications and/or custom requirements based on end applications

    End Applications

    • ASIC and FPGAs requiring high pin counts & electrical performance
    • CPUs driven by electrical performance
    • GPU (Graphics Processing Units) requiring electrical performance & efficient on-chip power distribution
    • PC chip sets and integrated graphics devices (IGP) driven by high I/O density
    • Tablet application processor (AP) devices driven by small form factor with high I/O density