Stacked Die Land Grid Array (FLGA-SD)
STATS ChipPAC's Stacked Die Land Grid Array (FLGA-SD) is available in 1.2mm (TFLGA-SD), 1.0mm (VFLGA-SD), 0.8mm (WFLGA-SD), 0.65mm (UFLGA-SD) & 0.5mm (XFLGA-SD) maximum thickness. STATS ChipPAC’s chip stack technology offers the flexibility of stacking 2 to 7 die in a single package. Die to die bonding capability enables device and signal integration to improve electrical performance and reduce overall package I/O requirements. Wafer thinning technology, overhang wire bond technology, and the use of spacers between stacked die provide the flexibility to stack almost any desirable configuration of die in one package. This capability uses existing assembly infrastructure, which results in more functional integration with lower overall package cost. The use of the latest packaging materials allows this package to meet JEDEC Moisture Resistance Test Level 2a with Lead-free reflow condition. This is an ideal package for cell phone applications where Digital, Flash, SRAM, PSRAM and Logic are stacked into a single package.
Features
- 2 to 7 die stack with spacer capability
- Flexible body sizes range from 4mm x 4mm to 12mm x 18mm
- Package height at 0.5, 0.65, 0.80, 1.0, 1.2, 1.4mm max
- Flexible die stacking options ("pyramid," "same die," etc.)
- 0.5mm minimum land pitch, flexible land pattern
- Memory, Logic, Analog and RF combinations
- JEDEC standard package outlines
- Die thinning to 40um (1.6mils) capability
- Low loop wire bonding; reverse and die to die
- Up to 2mm die overhang per side
- Halogen-free and Low-K wafer compatible BOM
- Film spacer capability for decreased die stack thickness
- Very thin substrate capability
- Capability to integrate discrete passives or integrated passive devices
- Solder bump capability
- Test capability
End Applications
- Handheld devices
- Wireless RF
- Analog
- ASIC
- Memory
- Simple PLDs