FiPoP

Fan-in Package-on-Package (FiPoP)

STATS ChipPAC’s Fan-in Package-on-Package (FiPoP) STATS ChipPAC’s Fan-in Package-on-Package, also known as Fi-PoP is a new 3D stackable packaging solution. The bottom FiPoP (FiPoPb) provides the flexibility to package a single device or multiple devices (logic, analog or memory), while providing land pads on the top center of the package to allow for another package or components to be reflowed on top. The FiPoPb can also incorporate a fully tested Internal Stacking Module (ISM) package. In addition, the FiPoPb can be smaller than current standard bottom PoP as interconnect is done by means of wire bonds, not solder balls at the edge of the bottom PoP. The package mounted on top of the FiPoPb can be a more conventional "off the shelf" center ball grid array package, such as a typical stacked die memory package or multiple packages or components. The top package can be significantly smaller than the current standard top PoP since it is no longer coupled to bottom package size by peripheral solder ball connections. The result is a flexible 3D stacked package solution with smaller footprint, less board mount issues (warpage) and lower overall cost.

Advantages

Fan-in PoP is a new Package-on-Package approach which addresses the demands of increased miniaturization, smaller footprint and increased device integration for advanced mobile applications. The versatile design of FiPoP accommodates multiple die and larger die sizes in a reduced footprint as compared to conventional PoP solutions, and the flexibility to stack off-the- shelf memory packages with center ball grid array patterns on the top surface.

The FiPoP still leverages the preferred business model of PoP in which logic device manufacturers provide the bottom package and memory device manufacturers typically provide the top package, allowing the end user to configure as needed tested good packages. The FiPoPb is an FBGA type package and the mountable surface on top is relatively free of warpage that can cause yield problems. The FiPoP construction allows for smaller bottom and top packages. The bottom and top package size can be reduced significantly (up to 25% and 65% respectively), thus taking up less board space and decreasing the overall cost of this PoP solution.

Features

  • Bottom FiPoP has exposed land pattern on center of top surface to allow mounting of top PoP
  • Bottom FiPoP allows for integration of stacked die or fully tested Internal Stacking Module (ISM) within
  • Bottom FiPoP height of less than 1.2mm (TFBGA-FiPoPb) with two dice stacked within
  • Top PoP is thinner, more conventional, center ball grid array
  • Top PoP height of less than 0.65mm or 0.8mm for 2 die stack (U/WFBGA-SD2)
  • Top PoP height of less than 0.80mm or 1.0mm for <4 die="" stack="" (w/vfbga-sd4)="">
  • Top PoP height of less than 1.0mm or 1.2mm for <7 die="" stack="" (v/tfbga-sd7)="">
  • Total stacked package height dependent on FiPoP configuration, but max 1.6mm typical (max 1.4mm possible)
  • Ni/Au or CuOSP on bottom pads of bottom PoP (PoPb), lead free ball options
  • Ni/Au or CuOSP on bottom pad of top PoP (PoPt), lead free ball options
  • Low stress and warpage packaging materials
  • Capable of device integration in bottom FiPoP

Test Services

  • Product Engineering support
  • Probe capability
  • Program generation/conversion

Applications

  • FiPoPb: Cellular phone and mobile device digital baseband processor, digital die stack, or digital + analog baseband die stack, digital + memory (ISM) stack, etc.
  • PoPt: Cellular phone and mobile device memory for digital processor and system memory (SDRAM, NOR/NAND Flash, SRAM)