Stacked Die and Stacked Packages
The 2D to 3D Technology Evolution
The market for portable and mobile data access devices is growing rapidly, driving the need for both increased functional convergence as well as increased packaging complexity and sophistication. Driven by the need for higher levels of integration, improved electrical performance, or reduction of timing delays, the need for shorter vertical interconnects is forcing a shift from 2D to 2.5D and 3D package designs. To meet this demand, semiconductor companies are turning to 3D integration technology to combine multiple chips with diverse functionality into increasingly smaller and smaller sizes. Technology integration is proceeding on three fronts:
package level with die and package stacking
wafer level with fan-in and fan-out wafer level packaging (FO WLP) such as embedded Wafer Level Ball Grid Array (eWLB)
silicon (Si) level with silicon via (TSV) and interposers
3D packaging provides a high level of functional integration in well established package families including BGAs and leadframe packages, by stacking die or stacking packages or a mix of both, and using a mix of assembly technologies including wire bonding, flip chip, surface mounted components and passive cooling.
The types of 3D packages are often characterized by how they are stacked, as chips, packages or passives. Stacked Die Packages consist of bare die stacked and interconnected using wire bond and flip chip connections in one standard package. The choice of the 3D packaging type is determined not only by the needs of the final product including footprint, profile and cost but the business model of procurement, assembly and ownership of the final module and the value added of the integration.
STATS ChipPAC offers a broad portfolio of stacked die and stacked packaging solutions:
Wafer Level IntegrationWafer level technologies such as eWLB are leading the way to the next level of thin packaging capability. They provide a robust packaging platform supporting very dense interconnection and routing of multiple die in very reliable, low-warpage 2.5D and 3D solutions. The use of these embedded fan-out wafer level packaging (FO WLP) in a side-by-side configuration to replace a stacked package configuration, or to utilize as the base for a 3D TSV configuration, is critical to enable a more cost effective mobile market capability.
Silicon Level IntegrationInterconnect density is increasing, driving smaller bond pad pitches, stacked die, mixed interconnect such as flip chip and wire bond in the same package, as well as advanced interconnect technologies such as interposers and Through Silicon Via (TSV). When combined with microbump bonding and advanced flip chip technology, TSV technology enables a higher level of functional integration and performance in a smaller form factor.