Design Services

Full-Service Packaging Design Centers

STATS ChipPAC offers full-service package Design Centers to help customers determine the optimum package for complex integrated circuits. STATS ChipPAC's design engineers will assist customers in designing a package substrate to meet the customer's power, ground and I/O requirements for each pin and conduct thermal and electrical simulations. STATS ChipPAC’s worldwide Design Centers will assist customers in generating the most appropriate package for their specific device.

STATS ChipPAC’s Design Center services include:
  • Customer-centric designers
  • Mobile design capability
  • Multiple design tools
  • Customer supplied designs integrated into the STATS ChipPAC’s Design System
  • Centralized design project management

Proven Experience

STATS ChipPAC's world class design team is experienced in the following types of package design:
 
  • System-in-Package (SiP)
  • Integrated Passive Device Design (IPD)
  • Chip Scale Module Package (CSMP)
  • Package-in-Package (PiP)
  • Package-on-Package (PoP)
  • Flip Chip
  • Stacked Die
  • Multi-layers up to 8 layers
  • Multi-Chip Modules
  • Fine Pitch Packages
  • High Ball Count
  • Land Grid Array
  • Enhanced BGA
  • Wafer Bumping

Probe station connected to a network analyzer for wafer level characterization 		 

Design for Performance

Today's packages must withstand stringent thermal and electrical requirements, while supporting the performance specification that the chip is designed to deliver. By designing a package while the chip is under development, STATS ChipPAC can help customers identify potential problems and develop solutions for products that will provide optimum performance once inside an actual system.

Streamlining the Design Documentation Process

STATS ChipPAC has taken a visionary approach to automating the design documentation process practiced in the semiconductor industry today, significantly reducing overall design cycle time and virtually eliminating manual entry. STATS ChipPAC’s integrated process leverages the strengths of advanced substrate design software and AutoCAD® while automating the documentation process. STATS ChipPAC is able to take complexe design and analysis data and transfer it quickly and easily into a format that suppliers can use. This automated process provides a variety of measurable benefits including:
  • Improved consistency and accuracy in bond diagram documentation
  • Documentation cycle time for the design process significantly reduced from an average of 4-8 hours down to 1 hour
  • 80% improvement in cycle time for all drawings generated
  • Designers have more time to concentrate on the design requirements and designing for best manufacturability while keeping in mind lowest substrate cost design practices

Responsive Cycle Times

The average STATS ChipPAC design cycle covers
  • 3 days: design
  • 1 day: design documentation and review
  • 1 day: manufacturing and vendor review

STATS ChipPAC also offers quick turn design cycles:
  • 48 hour design
  • 24 hour design documentation and review with manufacturing and vendor review

Broad Range of Design Tool Sets

Our Design Center facilities are equipped with state-of the-art design tools and hardware to support our customers' most difficult design issues:
  • Cadence: SiP and APD
  • Sigrity: UPD
  • Synopsys: Encore IC Packager
  • AutoDesk: AutoCad
  • Downstream: Cam350
  • ACS: BondGen & DocGen
  • Internally developed support tools
 

Additional Resources

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