System Level Electrical Analysis
High Speed Electrical Designs
Device operating frequencies in the GHz range or digital signals sub-ns edge rates make package interconnects electrically long in most traditional IC packages. Electrical performance prediction of such interconnect designs over a very wide band of frequencies, that encompasses the entire signal spectrum of interest, is critical for a successful design that works right the first time.
STATS ChipPAC uses Ansoft Links to translate complex package design layouts from Cadence APD or Synopsys Encore into Ansoft 3D models, with the desired levels of structural accuracy. The full wave 3D electromagnetic field solver Ansoft High Frequency Structure Simulator (HFSS) is then used to solve these structures and generate multi-port S-parameter behavioral models in frequency domain, from DC through multiple tens of GHz.
Signal Integrity and Power Integrity
System level performance metrics such as reflections, crosstalk, propagation delay, skew, etc. on a signal path and those such as voltage dips and bounces on a power delivery path are key indicators of the acceptability of a package design. It is important to verify if the package’s electrical performance stays within the margins allowed in the system noise and timing budgets. S-parameter models of interconnects or single/multi-section lumped element equivalent circuits fitted to those S-parameters can be directly plugged into system models for such prediction.
STATS ChipPAC uses Ansoft Designer to perform end-to-end system simulations, in time domain and/or frequency domain, that can include device models from customers/vendors and circuit/behavioral models for interconnects. The timing and noise data output from such simulations enables our customers to make intelligent package design tradeoffs quickly throughout the package development cycle.
Advanced Packaging Development
Challenging package designs for complex/miniature mixed signal systems need a chip-package co-design process in place. With the availability of extensive RF and DSP component libraries and Communication standard libraries for system level simulations, STATS ChipPAC can verify the electrical performance of an advanced package design such as a System-in-Package (SiP) or a Chip Scale Module Package (CSMP) and optimize it even before the customer completes his actual chip design. Such designs can be expected to perform the best, with just minor tweaks, as the customer completes his design and the device model becomes available for the final simulations.