Simplified Package Modeling - Electrical
Electrical Parasitic Data for Full Package Design
STATS ChipPAC has developed a leading-edge approach to full package electrical characterization that provides customers with early and accurate confirmation of electrical performance for the entire design. SPM-E allows full package electrical characterization for all types of leaded and array IC packages including plastic BGAs, enhanced BGAs, CSPs, multi-chip modules, and stacked die packages. Results for leaded packages and small array packages are delivered to the customer within 0.5 to 2 days of receiving the initial design; very large BGA designs take slightly longer.
SPM-E Process Flow
Data Output Formats
Another advantage of SPM-E is the variety of data output formats that are possible. The most general format is a data table that contains the self RLC values and the highest mutual RLC value for every net and plane. These can be separated into values for each component of the circuit (wire, trace, solderball, etc.) as needed by the customer.
The data can also be reformatted as requested by the customer. Available formats for use with customer specific equivalent circuit models include:
- Distributed RLC
- Lumped RLC
- Spice matrix