WLCSP (FIWLP Technology)

Wafer Level Chip Scale Package (WLCSP)


STATS ChipPAC offers high performance fan-in Wafer Level Chip Scale Packaing (WLCSP) solutions that provide significant package footprint reductions, lower cost, improved electrical performance, and a relatively simpler construction over conventional wirebond or interposer packaging.

Wafer Level Chip Scale Package (WLCSP) offers one of the most compact package footprints, providing increased functionality, improved thermal performance and finer pitch interconnection to the printed circuit board. Based on its small form factor and low cost, WLCSP has experienced significant growth driven aggressively by mobile consumer products because of the small form factor and high performance requirements. 

The WLCSP Advantage

WLCSP is the smallest possible package size since the final package is no larger than the required circuit area. All of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual chips to achieve a package that is essentially the same size as the die. The resultant package has dielectrics, thin film metals, and solder bumps directly on the surface of the die with no additional packaging. The basic structure of the WLCSP has an active surface with polymer coatings and bumps with bare silicon exposed on the remaining sides and back of the die. 

Advantages of fan-in Wafer Level Chip Scale Packaging (WLCSP) technology include

  • A true chip-scale package (CSP) where the package is the same size as the die
  • Advanced wafer level processes such as low cure temperture polymers and the use of copper for under bump metallization (UBM) and redistribution layers (RDL) to achieve higher densities and increased reliabilities
  • Repassivation, Redistribution, Bumping and IPD layer options available
  • A lower cost than other Ball Grid Array (BGA) and laminate-based CSPs

Encapsulation Provides Increased Reliability and Durability

The basic structure of WLCSP has an active surface with polymer coatings and bumps with bare silicon exposed on the remaining sides and back of the die.  As the industry transitions to more advanced node products, the exposed silicon that is inherent in the WLCSP design becomes more of a concern due to the fragile dielectric layers. As mobile device manufacturers tighten technical specifications to achieve new levels of reliability in their end products, more stringent inspections and product durability are required. STATS ChipPAC offers customers a solution called encapsulated Wafer Level Chip Scale Package (eWLCSP) which features a back and sidewall coating on the die for an increased level of durability and reliability over traditional WLCSP designs. The thin polymer casing on the back and four sidewalls of the die, providing mechanical robustness and resistance to chipping, cracking and handling damage, as well as improved long term reliability compared to traditional bare die WLCSP. 

WLCSP Market Applications & Drivers

A small, lightweight, high performance semiconductor solution, WLCSP is a compelling, cost effective solution for space constrained mobile applications and other portable consumer and industrial devices.