Wafer Level Packaging

Wafer Level Packaging

wafer level packaging

Your Go-To Provider for a Broad Range of Innovative Wafer Level Solutions

STATS ChipPAC offers wafer level technologies for the following package options:

  • eWLB (embedded Wafer Level Ball Grid Array)
  • eWLCSP (encapsulated Wafer Level Chip Scale Packages)
  • WLCSP (Wafer Level Chip Scale Packages)
  • IPD (Integrated Passive Devices)
  • TSV (Through Silicon Via)

    Today’s consumers are looking for powerful, multi-functional electronic devices with unprecedented performance and speed, yet small, thin and low cost. This creates complex technology and manufacturing challenges for semiconductor companies as they look for new ways to achieve greater performance and functionality in a small, thin, low cost device.  STATS ChipPAC is an industry leader in providing a comprehensive platform of wafer level technology solutions including Fan-in Wafer Level Packaging (FIWLP), Fan-out Wafer Level Packaging (FOWLP), Integrated Passive Devices (IPD) and Through Silicon Via (TSV). 

    Breakthrough FlexLineTM Manufacturing Approach

    Our innovative approach to wafer level manufacturing, known as the FlexLineTM method, provides customers freedom from wafer diameter constraints, while enabling supply chain simplification and significant cost reductions that are not possible with a conventional manufacturing flow.  This FlexLine manufacturing method is a significant paradigm shift from conventional wafer level manufacturing, and delivers an unmatched level of flexibility and cost savings for both Fan-In and Fan-Out wafer level packaging.

    The FlexLine approach provides freedom from wafer diameter constraints while enabling supply chain simplification and significant cost reductions not possible with conventional wafer level manufacturing. 

    Versatile technology platform for 2.5D and 3D integration

    Increasing demand for more advanced, smaller and lighter mobile products with superior functionality and lower overall cost is driving the need for more innovative and sophisticated packaging technologies. Fan-out wafer level packaging, also known as embedded Wafer Level Ball Grid Array (eWLB), provides a versatile platform for the semiconductor industry's evolution from single or multi-die 2D packages to 2.5D and 3D ICs or SiP configurations that deliver:
    • Higher performance
    • Higher frequencies
    • Higher bandwidth
    • Thinner package profiles