Press Release

STATS ChipPAC’s Advanced eWLB Provides a Versatile Integration Platform for the 2.5D and 3D Technology Evolution

eWLB packaging options expanded to include interposer technology, flip chip interconnect and complex 3D System-in-Package configurations


Singapore – 6 November 2012 – STATS ChipPAC Ltd. (“STATS ChipPAC” or the “Company” – SGX-ST: STATSChP), a leading semiconductor test and advanced packaging service provider, today announced that its expanded packaging options for advanced embedded Wafer Level Ball Grid Array (eWLB) technology provide a versatile platform for the semiconductor industry’s technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations.

The advancement of silicon scaling to 14 nanometer (nm) in support of higher performance, higher bandwidth and lower power consumption in portable and mobile devices is pushing the boundaries of emerging packaging technologies to smaller fan-out packaging designs with finer line/spacing as well as improved electrical performance and passive embedded technology capabilities. With its continuous innovation and extensive manufacturing experience in eWLB technology, STATS ChipPAC has established a flexible integration platform for 2.5D and 3D packaging at a lower overall cost with proven solutions that overcome manufacturing challenges pertaining to design, material compatibility and manufacturability in the industry today.

"We have taken the robust capabilities of eWLB and developed a solid integration platform for proven and successful 2.5D and 3D packaging integration. With our advanced eWLB technology we are able to provide our customers with the flexibility to integrate semiconductor die from diverse semiconductor processes and different silicon nodes into a cost effective interposer solution. We have also extended our eWLB capabilities into high-end flip chip Ball Grid Array (fcBGA) packaging to address future technical challenges in flip chip assembly as advanced technology nodes move below 28nm," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC.

Interposers are used to connect one active die to another in a 2.5D package configuration, enabling very dense interconnection with more effective heat dissipation, improved processing speed and the flexibility to integrate die from different manufacturing sources. While STATS ChipPAC continues to be in the forefront of the development and commercialisation of Through Silicon Via (TSV) as a 2.5D and 3D integration technology, the Company has in parallel developed new eWLB based interposers to support high density interconnection and routing of multiple dies in a proven, low-warpage packaging structure. The simplified materials supply chain and lower overall cost available with an eWLB based interposer provide a strong technology platform and path for customers to transition their devices to more advanced 2.5D and 3D packages.

With the inherent performance and cost advantages of eWLB, STATS ChipPAC is also effectively addressing some of the challenges in high end flip chip applications that require much finer bump pitches, higher input/output (I/O) densities and the elimination of stress on extreme low-k or ultra low-k (ELK/ULK) dielectric structures at advanced silicon wafer nodes. eWLB’s fan-out packaging approach with its inherently lower stress, larger pad pitch, and redistribution layer (RDL) allows higher integration and routing density in less metal layers in an fcBGA substrate. The fine line width and spacing capabilities of eWLB provides more flexibility in the package routing design and offers superior electrical performance, enabling the number of layers in the organic substrate of a standard fcBGA device to be reduced.

"We are leveraging our eWLB technology to drive substrate simplification and cost reduction while achieving tighter line/spaces in a range of 2.5D to 3D configurations that deliver product advantages to our customers in terms of higher performance, higher frequencies, higher bandwidth and thinner package profiles. With eWLB we have the flexibility to embed multiple active and passive components in the same wafer level package with a vertical 3D interconnection that can be achieved without the use of TSV," said Dr. Han.

STATS ChipPAC’s eWLB PoP solutions are available in either a single or double-sided configuration and provide a flexible integration platform for stacking a wide range of memory packages on top with a final stacked package height below 1.0mm. The number of interconnections between memory and processor can be up to 1024. The double-sided eWLB PoP technology features a flexible redistribution layer that can accommodate multiple active or passive devices in complex 3D SiP structures which enable very thin profiles, increased performance and superior warpage control.

STATS ChipPAC will be presenting the latest advancements in eWLB packaging and test at the International Wafer Level Packaging Conference that is being held from November 5th to 8th, 2012 in San Jose, California.

Forward-Looking Statements

Certain statements in this release are forward-looking statements that involve a number of risks and uncertainties that could cause actual events or results to differ materially from those described in this release. Factors that could cause actual results to differ include, but are not limited to, the timing and impact of the expected closure of the Thailand Plant as well as the estimated associated cost for the closure; the amount of the business interruption insurance claim due to flooding of the Thailand Plant; the ability to shift production to other manufacturing locations, shortages in supply of key components and disruption in supply chain; general business and economic conditions and the state of the semiconductor industry; prevailing market conditions; demand for end-use applications products such as communications equipment, consumer and multi-applications and personal computers; decisions by customers to discontinue outsourcing of test and packaging services; level of competition; our reliance on a small group of principal customers; our continued success in technological innovations; pricing pressures, including declines in average selling prices; intellectual property rights disputes and litigation; our ability to control operating expenses; our substantial level of indebtedness and access to credit markets; potential impairment charges; availability of financing; changes in our product mix; our capacity utilisation; delays in acquiring or installing new equipment; limitations imposed by our financing arrangements which may limit our ability to maintain and grow our business; returns from research and development investments; changes in customer order patterns; customer credit risks; disruption of our operations; loss of key management or other personnel; defects or malfunctions in our testing equipment or packages; rescheduling or cancelling of customer orders; adverse tax and other financial consequences if the taxing authorities do not agree with our interpretation of the applicable tax laws; classification of our Company as a passive foreign investment company; our ability to develop and protect our intellectual property; changes in environmental laws and regulations; exchange rate fluctuations; regulatory approvals for further investments in our subsidiaries; majority ownership by Temasek Holdings (Private) Limited (“Temasek”) that may result in conflicting interests with Temasek and our affiliates; unsuccessful acquisitions and investments in other companies and businesses; labour union problems in South Korea; uncertainties of conducting business in China and changes in laws, currency policy and political instability in other countries in Asia; natural calamities and disasters, including outbreaks of epidemics and communicable diseases; the continued trading and listing of our ordinary shares on the Singapore Exchange Securities Trading Limited (“SGX-ST”). You should not unduly rely on such statements. We do not intend, and do not assume any obligation, to update any forward-looking statements to reflect subsequent events or circumstances.

About STATS ChipPAC Ltd.

STATS ChipPAC Ltd. is a leading service provider of semiconductor packaging design, assembly, test and distribution solutions in diverse end market applications including communications, digital consumer and computing. With global headquarters in Singapore, STATS ChipPAC has design, research and development, manufacturing or customer support offices in 10 different countries. STATS ChipPAC is listed on the SGX-ST. Further information is available at www.statschippac.com. Information contained in this website does not constitute a part of this release.

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