PiP

Package-in-Package (PiP)


Package-in-Package (PiP) is an innovative family of 3D packages that stack packaged chips and bare chips into one JEDEC standard FBGA. A pre-tested Internal Stacking Module (ISM) Land Grid Array (LGA) and a BGA or a Known/Probed Good Die (KGD) are stacked and interconnected with wire bonding, then molded into a CSP that is indistinguishable from a conventional FBGA package.

A typical PiP integrates ASIC logic with memory chip(s), can have a minimal 12x12mm footprint, 1.2 to 1.4mm maximum thickness, and incorporate a 0.5mm to 0.4mm ball pitch.

The PiP package can be assembled and board mounted like a conventional FBGA package and has equivalent package and board level reliability.
PiP

Advantages

3D packaging is driven by wireless and consumer products that need package level functional integration in the smallest footprint, lowest profile and lowest cost CSP. Stacked die for Flash, SRAM and DRAM memories in a CSP are widely available today from memory suppliers but require KGD (especially for DRAM). As integration is extended to include complex and costly chips like ASIC in the same package with more Memory and Analog or RF chips, stacked packaging solutions are increasingly being utilized to maximize final test yield, expand supply chain and minimize the cost of ownership.

PiP enables new functionality in the shortest time-to-market and with minimum risk by stacking tested packages and known good logic or analog die sourced from the established supply chain. A lower PiP packaging cost, compared to the equivalent cost of separately packaged chips, and significantly reduced final test complexity both result in a module with lower cost of ownership.

Features

  • Package/die stack: 2 - 6 die stack
  • 10 x 10mm to 23 x 23mm body size
  • CSP package height at 1.2mm & 1.4mm max
  • 0.4mm to 0.8mm ball pitch
  • PIP body size can equal Internal Stacking Module (ISM) LGA size + 2mm
  • Tested memory + logic/analog/RF combinations
  • Allows flexible integration of tested memory & devices in small CSP package
  • JEDEC standard package outlines (for ISM and FBGA)
  • Thin die capability down to 40um
  • Thin mold cap down to 200um for ISM LGA
  • Low loop wire bonding, <50um

Test Services

  • Product Engineering support
  • Probe capability
  • Program generation/conversion
  • Drop Ship available

Applications

  • Integration of tested and burned-in memory with Baseband/ASIC/Graphics processor in small form factors
  • Competitive memory sourcing (packaged & tested)
  • Allows for flexible mixed technology integration
  • Portable electronics (Cellular phones, Gaming, PDAs, Digital Cameras, Camcorders, Wireless products)
  • 3D System in Package (SiP)
 

 

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