eWLB (FOWLP Technology)

Innovative Fan-out Wafer Level Technology



STATS ChipPAC offers a high performance fan-out wafer level packaging (FOWLP) solution that provides significant bandwidth, performance, form factor and cost benefits compared to other packaging technologies available today.

As an industry pioneer in FOWLP, STATS ChipPAC has been instrumental in developing fan-out technology into a mature platform that addresses the growing need for higher levels of integration, improved electrical performance and shorter vertical interconnects. 

Advantages of FOWLP, also known as embedded Wafer Level  Ball Grid Array (eWLB), technology include:  

  • Versatile platform for advanced system level integration
  • Highest integration density commercially available in the industry today
  • Flexibility to integrate die from diverse processes, manufacturing sources and silicon wafer nodes 
  • Excellent mechanical, electrical & thermal performance
  • Flexible, cost effective 2.5D and 3D solutions across a broad range of market segments and applications

    The Most Comprehensive Fan-Out Portfolio in the Industry

    An early industry adopter in 2008, STATS ChipPAC set an aggressive course in pushing the boundaries and developing advanced fan-out technology and manufacturing capabilities long before its peers.  STATS ChipPAC has driven a number of eWLB technology achievements such as dense vertical interconnections as high as 500 – 1,000 I/O, very fine line and widths spacing down to 2um/2um and ultra thin package profiles below 0.3mm (including solderball) for single packages and below 0.8mm for stacked packages with proven warpage control. 

    Our comprehensive Fan-out portfolios includes:
  • A wide range of small die, large die, flip chip, stacked or side-by-side multi-die and ultra-thin options
  • Single-sided, 1.5-sided and double-sided package configurations in face-to-face or face-to-back configurations
  • Integrated Passive Devices (IPD), embedded passives and active components
  • 2.5D eWLB interposer solutions (replaces stacked package configurations or to enable 3D TSV)
  • 3D System-in-Package (SiP) and Package-on-Package (PoP) solutions
  • The compelling performance, size and cost advantages of eWLB are accelerating the adoption of this advanced technology into new markets such as the Internet of Things (IoT) and wearable electronics, Micro-ElectroMechanical Systems (MEMS) and sensors, and automotive applications.

    Fan-out eWLB Advantages

    eWLB technology provides significant performance, size and cost advantages, compared to other technology available today:

    PERFORMANCE
    • Unprecedented flexibility in 2.5D & 3D integration with silicon partitioning capabilities
    • Advanced dielectric materials for highly reliable, power-efficient solutions
    • Strong electrical performance (capable to beyond 60GHz)
    • Highly effective heat dissipation for strong thermal performance
    • Known Good Die (KGD) process helps achieve strong yields (99.9%)

    FORM FACTOR
    • Maximum I/O density; 1.5-2X increase in routing density in the smallest, thinnest footprint commercially available today
    • Thin film processing enables very fine lines for X,Y routing, very fine via pitches & thin dielectrics
    • Die-to-die, die-to-passives, and passives-to-passives placement distances below 100um
    • Fine pitch copper (Cu) column bumps provide tighter pitch for 2.5D/3D designs
    • Industry’s thinnest 3D PoP solutions (ultra thin z-height of 0.3mm with stacked thickness down to 0.8mm height)

    COST
    • High volume manufacturing process enables scaling devices to larger carrier sizes for compelling cost reduction
    • Thin film interconnection offers lowest cost structure over competing advanced manufacturing approaches
    • Elimination of substrate results in a thinner package with lower warpage, simplifes supply chain & reduces costs
    • 2.5D and 3D options offers a more cost effective & infrastructure-friendly alternative to expensive TSV integration