Packaging Technology

Packaging Technology Overview

Your Go-To Provider for a Broad Range of Advanced and Standard IC Packages


Wafer Level Packaging Solutions
We offer a comprehensive platform of advanced and innovative wafer level technologies to meet the increasing market demand for next generation devices with higher levels of integration, increased functionality and compact sizes. These include:
  • Fan-in Wafer Level Packaging (FIWLP): eWLB
  • Fan-out Wafer Level Packaging (FOWLP): WLCSP and eWLCSP™
  • Integrated Passive Devices (IPD) 
  • Through Silicon Via (TSV)

Our comprehensive wafer level technology platform provides customers with a wide range of choices for 2D, 2.5D and 3D package integration in advanced mobile devices such as smartphones and tablets. Additionally, STATS ChipPAC’s innovative approach to WLCSP manufacturing, known as the FlexLine™ manufacturing method, is a significant paradigm shift from conventional wafer level manufacturing, and delivers an unmatched level of flexibility and cost savings for both Fan-In and Fan-Out wafer level packaging.

Flip Chip Solutions
We also offer a full suite of flip chip packages from large single die packages with passive components to modules and complex advanced 3D packaging, with a variety of low cost and innovative options. STATS ChipPAC's extensive flip chip portfolio includes:
  • fcBGA
  • fcFBGA
  • fcFBGA-Hybrid
  • fcLGA
  • Bare Die fcPoP
  • Molded Laser fcPoP

STATS ChipPAC offers full turnkey flip chip services ranging from design through production, including high speed, high pin count digital and RF testing.

Wirebond Solutions
STATS ChipPAC also offers a broad range of standard wirebond laminate and leadframe packages in single die, multi-die, stacked and thermally enhanced options, as well as a variety of memory card formats. These include:
  • Ball Grid Array laminate packages
  • Quad Flat Pack leadframe packages
  • Quad Flat No-Lead packages
  • Standard and advanced stacked packages including package-on-package (PoP) and package-in-package (PiP)
  • Memory cards

Copper Wirebond
In addition, STATS ChipPAC offers copper wirebond solutions in a wide range of leaded and laminate packages. With significant experience in copper wire conversions, STATS ChipPAC understands the requirements for successful copper wirebonding, offering a Best Value BOM (BVB) for each package for the most cost-effective copper wirebond solution.

Full Service Packaging Design
We collaborate with customers on die and package designs to provide the best possible products in terms of performance, quality, cycle time and cost. STATS ChipPAC’s full-service package Design Centers help customers determine the optimum package for complex integrated circuits, and can assist customers in designing the most appropriate package for their specific device.

 

 

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