STATS ChipPAC Taiwan (SCT) Profile
STATS ChipPAC Taiwan
No.176-5, 6 Ling
Lu Liao Ken, Hua-Lung Chun
Chiung-Lin, Hsin-Chu Hsien
Taiwan, R.O.C 307
Your IC testing partner in Taiwan!
A leading test house in Taiwan, STATS ChipPAC Taiwan
, a STATS ChipPAC company, offers proven expertise in mixed signal, digital, optical and RF devices. STATS ChipPAC Taiwan’s strategic relationship with the top semiconductor fabs and leading design houses in Taiwan provide customers with a one-stop solution and uninterrupted delivery of services for their products.
With a strong focus on wafer sort, CMOS Image Sensors and final test, this 218,149 square foot operation in Hsin-Chu Hsien Taiwan offers a full spectrum of turnkey services including incoming inspection, wafer probe, final test, dry bake, packing, tape and reel and drop shipment. Wafer probe capabilities include 200mm wafer, 300mm wafer, vertical probe and laser trim. Wafer Level Processing
As one of the fastest growing package types in the semiconductor industry, Wafer Level Packages (WLP) offer a small, lightweight, high performance device that is a cost effective solution for mobile and consumer applications. With state-of-the-art 300mm manufacturing capabilities and advanced process technologies such as low cure temperature polymers, under bump metallization (UBM) and redistribution layers (RDL), STATS ChipPAC Taiwan is a leader in wafer bump and WLP solutions.
Wafer level packages differ from laminate and leadframe based packages in that all of the manufacturing process steps are performed in parallel at the silicon wafer level rather than sequentially on individual semiconductor chips. A Wafer Level Chip Scale Package (WLCSP) is essentially the same size as the die, providing a high performance package in a more compact package footprint than conventional manufacturing processes. At STATS ChipPAC Taiwan, WLCSPs are manufactured with advanced process technologies such as electroplated copper RDL and UBM to achieve higher densities and increased reliability for customers. Wafer Bumping Services
Wafer bumping is a process in which interconnections (solder “bumps” or “balls”) are formed on an entire wafer prior to dicing. The use of wafer bumping is driven either by the need for high performance, high I/O densities, small form factor or array interconnect requirements. STATS ChipPAC Taiwan offers 300mm solder bump and copper column bumping services. 300mm Solder Bump
STATS ChipPAC Taiwan’s world-class solder bumping line offers high volume production capability for 300mm wafers. This state-of-the-art facility provides eutectic and solder alloy (low alpha) and leadfree soldering bumping. Copper Column Bump
Copper column bump provides a high performance, cost effective solution for advanced silicon fab nodes. STATS ChipPAC Taiwan is experienced in copper column bump technology which enables a higher I/O density in very fine bump pitches down to 80um with a higher resistance to electromigration.
- ISO 9001
- TS 16949
- ISO 14001
- OHSAS 18001
- Sony Green Partner